[PATCH] D119171: [SelectionDAG][RISCV][ARM][PowerPC][X86][WebAssembly] Change default abs expansion to use sra (X, size(X)-1); sub (xor (X, Y), Y).

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: spatel, RKSimon, lebedev.ri, efriedma, nemanjai, tlively.
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Previous we used sra (X, size(X)-1); xor (add (X, Y), Y).

By placing sub at the end, we allow RISCV to combine sign_extend_inreg
with it to form subw.

Some X86 tests for Z - abs(X) seem to have improved as well.

Other targets look to be a wash.

I had to modify ARM's abs matching code to match from sub instead of
xor. Maybe instead ISD::ABS should be made legal. I'll try that in
parallel to this patch.

This is an alternative to D119099 <https://reviews.llvm.org/D119099> which was focused on RISCV only.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D119171

Files:
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
  llvm/test/CodeGen/PowerPC/ppc64-P9-vabsd.ll
  llvm/test/CodeGen/RISCV/rv32zbb.ll
  llvm/test/CodeGen/RISCV/rv64zbb.ll
  llvm/test/CodeGen/Thumb/iabs.ll
  llvm/test/CodeGen/Thumb/optionaldef-scheduling.ll
  llvm/test/CodeGen/Thumb2/abs.ll
  llvm/test/CodeGen/WebAssembly/PR41149.ll
  llvm/test/CodeGen/X86/abs.ll
  llvm/test/CodeGen/X86/combine-abs.ll
  llvm/test/CodeGen/X86/iabs.ll
  llvm/test/CodeGen/X86/neg-abs.ll
  llvm/test/CodeGen/X86/viabs.ll
  llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/basic.ll.expected

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