[PATCH] D119110: [RISCV] support vwmulsu_vx when one input is a scalar splat

Chenbing.Zheng via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Sun Feb 13 17:27:22 PST 2022


Chenbing.Zheng added a comment.

In D119110#3316555 <https://reviews.llvm.org/D119110#3316555>, @craig.topper wrote:

> I posted an alternative version as D119622 <https://reviews.llvm.org/D119622>. It makes use of MaskedValueIsZero like is used for vwmulu. A new DAG combine for VMV_V_X_VL is used to remove unnecessary AND instructions.

Thanks, it is a more generic version~


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  https://reviews.llvm.org/D119110/new/

https://reviews.llvm.org/D119110



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