[PATCH] D119090: [X86] Improve uniform funnelshift/rotation amount handling

[Phoebe Wang via Phabricator via llvm-commits]

pengfei accepted this revision.
pengfei added a comment.
This revision is now accepted and ready to land.

LGTM with some nits.



================
Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:25713-25714
+
+  // Change opcode to non-immediate version.
+  Opc = getTargetVShiftUniformOpcode(Opc, true);
+
----------------
Move it close to its use?


================
Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:25725
+  bool IsMasked = false;
+  if (AmtVT.getScalarSizeInBits() < 64) {
+    if (ShAmt.getOpcode() == ISD::BUILD_VECTOR ||
----------------
Can we handle for 64 bit now? Should simply add an assert instead?


================
Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:25761-25762
+    if (Subtarget.hasSSE41())
+      ShAmt = DAG.getNode(ISD::ZERO_EXTEND_VECTOR_INREG, SDLoc(ShAmt),
+                          MVT::v2i64, ShAmt);
+    else {
----------------
Should move comment in line 25758 here?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D119090/new/

https://reviews.llvm.org/D119090