[PATCH] D119435: [Support][AArch64] Detect a few more host CPU features on AArch64

Fri Feb 11 18:22:40 PST 2022

danilaml added a comment.

In D119435#3316044 <https://reviews.llvm.org/D119435#3316044>, @tschuett wrote:

> https://github.com/torvalds/linux/blob/master/Documentation/arm64/cpu-feature-registers.rst
> Is similar to how Intel is doing feature detection.

Just as I suspected, not accessible from userspace:

> Access to these system registers is restricted from EL0 and there is no reliable way for an application to extract this information to make better decisions at runtime.

================
Comment at: llvm/lib/Support/Host.cpp:1709
                                    .Case("crc32", "crc")
+                                   .Case("atomics", "lse")
+                                   .Case("sve", "sve")
----------------
nickdesaulniers wrote:
> The Features line of the cpus in my pixel 6 pro have `atomics` (but not sve or sve2). (I don't have an aarch64 host machine for development, yet)
> 
> Example:
> ```
> Features        : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp
> ```
> 
> to prevent this from getting out of date again, I wonder if we should assert in the default case (and add the rest)?
> 
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/include/uapi/asm/hwcap.h seems to describe these.
What do you mean by "assert in the default case"? Assert if we encounter unknown feature? Feels too restrictive. I don't think there is a 1-to-1 between all HWCAP stuff and LLVM features (although I might be wrong), i.e. is uscat == LSE2 or something else?

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https://reviews.llvm.org/D119435