[PATCH] D119581: [AMDGPU] Divergence-driven abs instruction selection

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIInstructions.td:2255
+def : GCNPat<
+  (i32 (DivergentUnaryFrag<abs> i32:$src)),
+  (V_MAX_I32_e64 (V_SUB_U32_e32 (i32 0), $src), $src)>{
----------------
Don't you need to add complexity to this pattern?


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Comment at: llvm/test/CodeGen/AMDGPU/divergence-driven-abs.ll:1
+; RUN:  llc -march=amdgcn -stop-after=amdgpu-isel < %s | FileCheck -enable-var-scope -check-prefixes=GCN %s
+
----------------
Fix file mode.


================
Comment at: llvm/test/CodeGen/AMDGPU/divergence-driven-abs.ll:1
+; RUN:  llc -march=amdgcn -stop-after=amdgpu-isel < %s | FileCheck -enable-var-scope -check-prefixes=GCN %s
+
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rampitec wrote:
> Fix file mode.
Add a run line for gfx900 to check opcode w/o carry.


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Comment at: llvm/test/CodeGen/AMDGPU/divergence-driven-abs.ll:15
+; FUNC-LABEL: {{^}}v_abs_i32:
+; GCN: V_MAX_I32_e64
+define amdgpu_kernel void @v_abs_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %src) nounwind {
----------------
Check v_sub as well, differently for SI and GFX9.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D119581/new/

https://reviews.llvm.org/D119581