[PATCH] D119105: [DAGCombiner][AArch64] Enhance to fold CSNEG into CSINC instruction

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

Thanks. I think something might not be right in the new logic.
`(add y, (csneg 1, c, eq))` is `eq ? y+1 : y-c`. Which should be `(csinc (sub y, c), y, ne)`
`(add y, (csneg c, -1, eq))` is `eq ? y+c : y+1`. Which should be `(csinc (add y, c), y, eq)`
I may be wrong with all these double negatives though, correct me if that looks wrong. I would expect the assembly to be `sub w8, w1, #1; csinc w0, w8, w1`


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  https://reviews.llvm.org/D119105/new/

https://reviews.llvm.org/D119105