[PATCH] D119072: [DAGCombine] Move AVG combine to SimplifyDemandBits

Fri Feb 11 08:55:10 PST 2022

dmgreen added a comment.

In D119072#3314045 <https://reviews.llvm.org/D119072#3314045>, @RKSimon wrote:

> You've made this a blocker to some other patches - is it necessary or just nice to have?

No I don't think so - same as the comment in https://reviews.llvm.org/D119073#3308941, it should be OK in the other order, this is just the order I happened to have it locally, so the tests might be different. This gives better codegen, so I would like to get it in.

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Comment at: llvm/test/CodeGen/AArch64/arm64-vhadd.ll:1197
+; CHECK-NEXT:    xtn.8b v0, v0
 ; CHECK-NEXT:    ret
   %sextsrc1 = ashr <8 x i16> %src1, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
----------------
RKSimon wrote:
> regression?
The usra is generally a more expensive operation, that gets split into a shift and an add on the CPU's I looked at. It will be larger for codesize, but shouldn't be slower.

I left the example in because it shows some of the potential disadvantage with using sign/known bits. It's better in general, but there may be places with extra extends.

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D119072/new/

https://reviews.llvm.org/D119072