[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Shao-Ce SUN via Phabricator via llvm-commits]

achieveartificialintelligence marked an inline comment as done.
achieveartificialintelligence added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:557
+
+let RegInfos = RegInfoByHwMode<[RV64], [RegInfo<64, 64, 64>]> in
+def GPRPF64 : RegisterClass<"RISCV", [f64], 64, (add
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Jim wrote:
> Is register pair only on RV32 for used as f64?
Yes.


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  https://reviews.llvm.org/D93298/new/

https://reviews.llvm.org/D93298