[PATCH] D119424: [AArch64][SVE] Invert VSelect operand order and condition for predicated arithmetic operations

Matt Devereau via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Feb 11 05:09:31 PST 2022

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MattDevereau added a comment.

@paulwalker-arm I replaced `ISD::FMUL` etc with `AArch64::FMUL_PRED` however it failed to do the combine afterwards


Repository:
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  https://reviews.llvm.org/D119424/new/

https://reviews.llvm.org/D119424

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