[PATCH] D119210: [RISCV] Recover the implication between Zve* extensions and the V extension.

[Yueh-Ting Chen via Phabricator via llvm-commits]

eopXD accepted this revision.
eopXD added a comment.
This revision is now accepted and ready to land.

LGTM.
For the record the implication in this patch correspond to the note under v-spec <https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#183-v-vector-extension-for-application-processors>:

> As is the case with other RISC-V extensions, it is valid to include overlapping extensions in the same ISA string. For example, RV64GCV and RV64GCV_Zve64f are both valid and equivalent ISA strings, as is RV64GCV_Zve64f_Zve32x_Zvl128b.


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  https://reviews.llvm.org/D119210/new/

https://reviews.llvm.org/D119210