[PATCH] D119424: [AArch64][SVE] Invert VSelect operand order and condition for predicated arithmetic operations

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added a comment.

Do you want to perform this combine for all vector types?  You want the combine for an SVE specific reason and thus I'm wondering if it's better to restrict the combine to scalable vectors? Also, do use counts need to play a role here? I'm thinking that you might not want to flip the condition if it means generating additional compare instructions.


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  https://reviews.llvm.org/D119424/new/

https://reviews.llvm.org/D119424