[llvm] 74aa44a - [X86] Zero out the 32-bit GPRs explicitly

[Bill Wendling via llvm-commits]

Author: Bill Wendling
Date: 2022-02-10T23:09:00-08:00
New Revision: 74aa44a887732a09bce524cbc6d5039333ddffbe

URL: https://github.com/llvm/llvm-project/commit/74aa44a887732a09bce524cbc6d5039333ddffbe
DIFF: https://github.com/llvm/llvm-project/commit/74aa44a887732a09bce524cbc6d5039333ddffbe.diff

LOG: [X86] Zero out the 32-bit GPRs explicitly

This should ensure that only the 32-bit xors are emitted, and not the
64-bit xors.

Differential Revision: https://reviews.llvm.org/D119523

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86FrameLowering.cpp
    llvm/test/CodeGen/X86/zero-call-used-regs.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/X86FrameLowering.cpp b/llvm/lib/Target/X86/X86FrameLowering.cpp
index 2a798e2e62cb8..30f621a13b828 100644
--- a/llvm/lib/Target/X86/X86FrameLowering.cpp
+++ b/llvm/lib/Target/X86/X86FrameLowering.cpp
@@ -538,14 +538,18 @@ void X86FrameLowering::emitZeroCallUsedRegs(BitVector RegsToZero,
   }
 
   // For GPRs, we only care to clear out the 32-bit register.
+  BitVector GPRsToZero(TRI->getNumRegs());
   for (MCRegister Reg : RegsToZero.set_bits())
     if (TRI->isGeneralPurposeRegister(MF, Reg)) {
-      Reg = getX86SubSuperRegisterOrZero(Reg, 32);
-      for (const MCPhysReg &Reg : TRI->sub_and_superregs_inclusive(Reg))
-        RegsToZero.reset(Reg);
-      RegsToZero.set(Reg);
+      GPRsToZero.set(getX86SubSuperRegisterOrZero(Reg, 32));
+      RegsToZero.reset(Reg);
     }
 
+  for (MCRegister Reg : GPRsToZero.set_bits())
+    BuildMI(MBB, MBBI, DL, TII.get(X86::XOR32rr), Reg)
+        .addReg(Reg, RegState::Undef)
+        .addReg(Reg, RegState::Undef);
+
   // Zero out registers.
   for (MCRegister Reg : RegsToZero.set_bits()) {
     if (ST.hasMMX() && X86::VR64RegClass.contains(Reg))
@@ -553,9 +557,7 @@ void X86FrameLowering::emitZeroCallUsedRegs(BitVector RegsToZero,
       continue;
 
     unsigned XorOp;
-    if (TRI->isGeneralPurposeRegister(MF, Reg)) {
-      XorOp = X86::XOR32rr;
-    } else if (X86::VR128RegClass.contains(Reg)) {
+    if (X86::VR128RegClass.contains(Reg)) {
       // XMM#
       if (!ST.hasSSE1())
         continue;

diff  --git a/llvm/test/CodeGen/X86/zero-call-used-regs.ll b/llvm/test/CodeGen/X86/zero-call-used-regs.ll
index 5eafb3b26fce6..146f5e37d9a10 100644
--- a/llvm/test/CodeGen/X86/zero-call-used-regs.ll
+++ b/llvm/test/CodeGen/X86/zero-call-used-regs.ll
@@ -156,6 +156,8 @@ define dso_local i32 @all_arg(i32 returned %x) local_unnamed_addr #0 "zero-call-
 ; X86-64-NEXT:    xorl %edi, %edi
 ; X86-64-NEXT:    xorl %edx, %edx
 ; X86-64-NEXT:    xorl %esi, %esi
+; X86-64-NEXT:    xorl %r8d, %r8d
+; X86-64-NEXT:    xorl %r9d, %r9d
 ; X86-64-NEXT:    xorps %xmm0, %xmm0
 ; X86-64-NEXT:    xorps %xmm1, %xmm1
 ; X86-64-NEXT:    xorps %xmm2, %xmm2
@@ -164,8 +166,6 @@ define dso_local i32 @all_arg(i32 returned %x) local_unnamed_addr #0 "zero-call-
 ; X86-64-NEXT:    xorps %xmm5, %xmm5
 ; X86-64-NEXT:    xorps %xmm6, %xmm6
 ; X86-64-NEXT:    xorps %xmm7, %xmm7
-; X86-64-NEXT:    xorl %r8d, %r8d
-; X86-64-NEXT:    xorl %r9d, %r9d
 ; X86-64-NEXT:    retq
 
 entry:
@@ -231,6 +231,14 @@ define dso_local i32 @all(i32 returned %x) local_unnamed_addr #0 "zero-call-used
 ; X86-64-NEXT:    xorl %edi, %edi
 ; X86-64-NEXT:    xorl %edx, %edx
 ; X86-64-NEXT:    xorl %esi, %esi
+; X86-64-NEXT:    xorl %r8d, %r8d
+; X86-64-NEXT:    xorl %r9d, %r9d
+; X86-64-NEXT:    xorl %r10d, %r10d
+; X86-64-NEXT:    xorl %r11d, %r11d
+; X86-64-NEXT:    xorl %r12d, %r12d
+; X86-64-NEXT:    xorl %r13d, %r13d
+; X86-64-NEXT:    xorl %r14d, %r14d
+; X86-64-NEXT:    xorl %r15d, %r15d
 ; X86-64-NEXT:    xorps %xmm0, %xmm0
 ; X86-64-NEXT:    xorps %xmm1, %xmm1
 ; X86-64-NEXT:    xorps %xmm2, %xmm2
@@ -247,14 +255,6 @@ define dso_local i32 @all(i32 returned %x) local_unnamed_addr #0 "zero-call-used
 ; X86-64-NEXT:    xorps %xmm13, %xmm13
 ; X86-64-NEXT:    xorps %xmm14, %xmm14
 ; X86-64-NEXT:    xorps %xmm15, %xmm15
-; X86-64-NEXT:    xorl %r8d, %r8d
-; X86-64-NEXT:    xorl %r9d, %r9d
-; X86-64-NEXT:    xorl %r10d, %r10d
-; X86-64-NEXT:    xorl %r11d, %r11d
-; X86-64-NEXT:    xorl %r12d, %r12d
-; X86-64-NEXT:    xorl %r13d, %r13d
-; X86-64-NEXT:    xorl %r14d, %r14d
-; X86-64-NEXT:    xorl %r15d, %r15d
 ; X86-64-NEXT:    retq
 
 entry: