[PATCH] D119436: RFC: RegAlloc: Avoid repeated calls to freezeReservedRegs

[Jay Foad via Phabricator via llvm-commits]

foad created this revision.
foad added reviewers: arsenm, t.p.northover, piotr.
Herald added subscribers: hiraditya, kristof.beyls, tpr, qcolombet, MatzeB.
foad requested review of this revision.
Herald added subscribers: llvm-commits, wdng.
Herald added a project: LLVM.

With split register allocation, only call MRI->freezeReservedRegs if
they are not already frozen. This makes a measurable difference on
AMDGPU where regalloc is split in two and
SIRegisterInfo::getReservedRegs is expensive due to the large register
file and many subregs.

I measured a ~5% speed up with:

$ cat empty.ll
define void @f() {

  ret void

}
$ perf stat -r 1000 -- llc -march amdgcn -mcpu gfx1030 empty.ll -filetype null

FIXME: The assertion I added fails on a few AArch64 CodeGen tests,
apparently because AArch64RegisterInfo::hasBasePointer changes after
FinalizeISel. How should this be handled? Is the target required to
call freezeReservedRegs again whenever the set of reserved regs might
have changed?


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D119436

Files:
  llvm/lib/CodeGen/RegAllocBase.cpp


Index: llvm/lib/CodeGen/RegAllocBase.cpp
===================================================================
--- llvm/lib/CodeGen/RegAllocBase.cpp
+++ llvm/lib/CodeGen/RegAllocBase.cpp
@@ -61,7 +61,16 @@
   VRM = &vrm;
   LIS = &lis;
   Matrix = &mat;
-  MRI->freezeReservedRegs(vrm.getMachineFunction());
+  if (MRI->reservedRegsFrozen()) {
+#ifndef NDEBUG
+    BitVector OldReservedRegs(MRI->getReservedRegs());
+    MRI->freezeReservedRegs(vrm.getMachineFunction());
+    assert(OldReservedRegs == MRI->getReservedRegs() &&
+           "Frozen reserved regs should not have changed!");
+#endif
+  } else {
+    MRI->freezeReservedRegs(vrm.getMachineFunction());
+  }
   RegClassInfo.runOnMachineFunction(vrm.getMachineFunction());
 }
 


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