[llvm] 6241f7d - [FastISel] Remove redundant reg class check (NFC)

[Nikita Popov via llvm-commits]

Author: Nikita Popov
Date: 2022-02-10T14:10:00+01:00
New Revision: 6241f7dee0a776521fbdc6a0000488d45bda1542

URL: https://github.com/llvm/llvm-project/commit/6241f7dee0a776521fbdc6a0000488d45bda1542
DIFF: https://github.com/llvm/llvm-project/commit/6241f7dee0a776521fbdc6a0000488d45bda1542.diff

LOG: [FastISel] Remove redundant reg class check (NFC)

SrcVT and DstVT are the same in this branch, as such their register
classes will also be the same.

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/FastISel.cpp

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
index d8ef79fe9a7bc..263fcc6e72bc3 100644
--- a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
@@ -1434,14 +1434,9 @@ bool FastISel::selectBitCast(const User *I) {
   // First, try to perform the bitcast by inserting a reg-reg copy.
   Register ResultReg;
   if (SrcVT == DstVT) {
-    const TargetRegisterClass *SrcClass = TLI.getRegClassFor(SrcVT);
-    const TargetRegisterClass *DstClass = TLI.getRegClassFor(DstVT);
-    // Don't attempt a cross-class copy. It will likely fail.
-    if (SrcClass == DstClass) {
-      ResultReg = createResultReg(DstClass);
-      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
-              TII.get(TargetOpcode::COPY), ResultReg).addReg(Op0);
-    }
+    ResultReg = createResultReg(TLI.getRegClassFor(DstVT));
+    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
+            TII.get(TargetOpcode::COPY), ResultReg).addReg(Op0);
   }
 
   // If the reg-reg copy failed, select a BITCAST opcode.