[PATCH] D119428: [AArch64][SVE] Fix selection failure caused by fp/int convert using non-Neon types

[Bradley Smith via Phabricator via llvm-commits]

bsmith created this revision.
bsmith added reviewers: paulwalker-arm, peterwaller-arm, sdesmalen.
Herald added subscribers: psnobl, hiraditya, kristof.beyls, tschuett.
Herald added a reviewer: efriedma.
bsmith requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

Fixes: #53679


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D119428

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/sve-fixed-length-fp-convert.ll


Index: llvm/test/CodeGen/AArch64/sve-fixed-length-fp-convert.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AArch64/sve-fixed-length-fp-convert.ll
@@ -0,0 +1,25 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s | FileCheck %s
+
+target triple = "aarch64-unknown-linux-gnu"
+
+; Ensure we don't crash when trying to combine fp<->int conversions
+define void @fp_convert_combine_crash(<8 x float> *%a, <8 x i32> *%b) #0 {
+; CHECK-LABEL: fp_convert_combine_crash:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p0.s
+; CHECK-NEXT:    fmov z1.s, #8.00000000
+; CHECK-NEXT:    ld1w { z0.s }, p0/z, [x0]
+; CHECK-NEXT:    fmul z0.s, z0.s, z1.s
+; CHECK-NEXT:    fcvtzs z0.s, p0/m, z0.s
+; CHECK-NEXT:    st1w { z0.s }, p0, [x1]
+; CHECK-NEXT:    ret
+  %f = load <8 x float>, <8 x float>* %a
+  %mul.i = fmul <8 x float> %f, <float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00,
+                                 float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00>
+  %vcvt.i = fptosi <8 x float> %mul.i to <8 x i32>
+  store <8 x i32> %vcvt.i, <8 x i32>* %b
+  ret void
+}
+
+attributes #0 = { vscale_range(2,2) "target-features"="+sve" }
Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -13739,6 +13739,9 @@
       Op.getOpcode() != ISD::FMUL)
     return SDValue();
 
+  if (Op.getValueSizeInBits().getFixedSize() > 128)
+    return SDValue();
+
   SDValue ConstVec = Op->getOperand(1);
   if (!isa<BuildVectorSDNode>(ConstVec))
     return SDValue();


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