[PATCH] D119334: [AArch64][SVE] Fold away SETCC if original input was predicate vector.

[David Sherwood via Phabricator via llvm-commits]

david-arm added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:17092
+      LHS->getOperand(0)->getValueType(0) == N->getValueType(0)) {
+    //    setcc_merge_zero(
+    //       pred, extend(setcc_merge_zero(CC, pred, ...)), != splat(0))
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nit: Hi @sdesmalen, this is only a minor issue, but the notation in the comments is a little inconsistent in places. I found this a little confusing at first. For example, in some places it's

  setcc_merge_zero(pred, LHS, RHS != 0)

and in others it's

  setcc_merge_zero(CC, pred, ...)

Is it worth just sticking to a single notation for clarity?


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:17108
+    // -> nxvNi1 and(pred, ...)
+    if (DCI.isAfterLegalizeDAG())
+      return DAG.getNode(ISD::AND, SDLoc(N), N->getValueType(0),
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Is it worth adding a comment here explaining briefly why it's after legalisation?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D119334/new/

https://reviews.llvm.org/D119334