[PATCH] D118845: [RISCV] Move the creation of VLMaxSentinel to isel. Use X0 during lowering.

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck accepted this revision.
frasercrmck added a comment.
This revision is now accepted and ready to land.

Thanks for a clarifying; I was also unsure as to the motivation, if I'm honest. LGTM too.



================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td:681
               (vti.Wti.Vector (extop (vti.Vti.Vector vti.Vti.RegClass:$rs1)))),
-          (riscv_vmset_vl VLMax),
-          VLMax)),
+          (riscv_vmset_vl X0),
+          X0)),
----------------
I was curious when this landed: can't we use `true_mask` here? If the length of this vmset isn't VLMax we can still choose the undefined lanes to be 1, can't we?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D118845/new/

https://reviews.llvm.org/D118845