[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:555
+def GPRF64  : RegisterClass<"RISCV", [f64], 64, (add GPR)>;
+def GPRPF64 : RegisterClass<"RISCV", [f64], 64, (add
+    X10_PD, X12_PD, X14_PD, X16_PD,
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Jim wrote:
> Is XLenRI correct for GPRPF64? RV32 has size 32.
I'm not sure the RegInfos are correct for the other classes either. The RegInfos override the register size, the spill size, and spill alignment. I think those should all be based on the FP type.

So I don't think any of these should have a RegInfos.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93298/new/

https://reviews.llvm.org/D93298