[PATCH] D119355: [SVE] Remove AArch64ISD::ADD_PRED and AArch64ISD::SUB_PRED.

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm created this revision.
Herald added subscribers: ctetreau, psnobl, hiraditya, kristof.beyls, tschuett.
Herald added a reviewer: efriedma.
paulwalker-arm requested review of this revision.
Herald added subscribers: llvm-commits, alextsao1999.
Herald added a project: LLVM.

These nodes provide an indirection that is not necessary because
SVE has unpredicated add/sub instructions and there's no downside
to using them for partial register operations. In fact, the test
changes show that unifying how fixed-length and scalable vector
add/sub are lowered enables better use of existing isel patterns.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D119355

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-arith.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-extends.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-immediates.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-reduce.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-rem.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-limit-duplane.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-masked-scatter.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-optimize-ptrue.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-permute-zip-uzp-trn.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-trunc.ll
  llvm/test/CodeGen/AArch64/sve-ld-post-inc.ll
  llvm/test/CodeGen/AArch64/sve-vscale-attr.ll

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