[PATCH] D119303: [RISCV] Lower VECTOR_SPLICE to RVV instructions.

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added a comment.

A few nits. I think the commit message/description could be more explicit that this is only for scalable-vector splices. Fixed-length vectors are technically supported by the intrinsic, even if they're not recommended.



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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:5557
+  int64_t ImmValue = cast<ConstantSDNode>(Op.getOperand(2))->getSExtValue();
+  // The operand is a TargetConstant, we need to rebuild it as a regular
+  // constant.
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This comment seems not to reflect the code on the following lines.


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Comment at: llvm/test/CodeGen/RISCV/rvv/vector-splice.ll:4
+
+; Tests assume VLEN=128 or vscale_range_min=2.
+
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Do they?


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  https://reviews.llvm.org/D119303/new/

https://reviews.llvm.org/D119303