[PATCH] D76007: [TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

In D76007#3287539 <https://reviews.llvm.org/D76007#3287539>, @lewis-revill wrote:

> In D76007#3249742 <https://reviews.llvm.org/D76007#3249742>, @arsenm wrote:
>
>> I'm not sure I understand why the RegisterBankInfo needs to be aware of the hwmode. HWmode changes the size of the classes during selection, but the registerbankinfo just needs to assign sizes to banks. The concrete classes don't matter so much
>
> Unsure if I understood your comment! The patch itself was necessary since the assignment of a single size to each register bank is wrong for targets with different register sizes for different hardware modes. If the RegisterBankInfo is aware of the hardware mode then we can query what the size of a given register bank actually is for the current hardware mode. The register bank array itself is also constructed once by TableGen so we can't change sizes when they're constructed. And it isn't safe to change the size after construction.

Register banks do not have sizes. A register bank mapping is a bank plus a size/offset that you can change based on the target's size, not part of the bank itself.


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https://reviews.llvm.org/D76007