[llvm] 60745fb - [VP] llvm.vp.fneg intrinsic and LangRef
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 9 08:05:23 PST 2022
Author: Craig Topper
Date: 2022-02-09T07:54:36-08:00
New Revision: 60745fb16fb423a505fdaeadc499f6b5a8344f7d
URL: https://github.com/llvm/llvm-project/commit/60745fb16fb423a505fdaeadc499f6b5a8344f7d
DIFF: https://github.com/llvm/llvm-project/commit/60745fb16fb423a505fdaeadc499f6b5a8344f7d.diff
LOG: [VP] llvm.vp.fneg intrinsic and LangRef
Reviewed By: frasercrmck
Differential Revision: https://reviews.llvm.org/D119262
Added:
Modified:
llvm/docs/LangRef.rst
llvm/include/llvm/IR/Intrinsics.td
llvm/include/llvm/IR/VPIntrinsics.def
llvm/unittests/IR/VPIntrinsicTest.cpp
Removed:
################################################################################
diff --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst
index fab605ffb4750..9b819dcd94196 100644
--- a/llvm/docs/LangRef.rst
+++ b/llvm/docs/LangRef.rst
@@ -18599,7 +18599,7 @@ operation.
Semantics:
""""""""""
-The '``llvm.vp.fadd``' intrinsic performs floating-point addition (:ref:`add <i_fadd>`)
+The '``llvm.vp.fadd``' intrinsic performs floating-point addition (:ref:`fadd <i_fadd>`)
of the first and second vector operand on each enabled lane. The result on
disabled lanes is undefined. The operation is performed in the default
floating-point environment.
@@ -18648,7 +18648,7 @@ operation.
Semantics:
""""""""""
-The '``llvm.vp.fsub``' intrinsic performs floating-point subtraction (:ref:`add <i_fsub>`)
+The '``llvm.vp.fsub``' intrinsic performs floating-point subtraction (:ref:`fsub <i_fsub>`)
of the first and second vector operand on each enabled lane. The result on
disabled lanes is undefined. The operation is performed in the default
floating-point environment.
@@ -18697,7 +18697,7 @@ operation.
Semantics:
""""""""""
-The '``llvm.vp.fmul``' intrinsic performs floating-point multiplication (:ref:`add <i_fmul>`)
+The '``llvm.vp.fmul``' intrinsic performs floating-point multiplication (:ref:`fmul <i_fmul>`)
of the first and second vector operand on each enabled lane. The result on
disabled lanes is undefined. The operation is performed in the default
floating-point environment.
@@ -18746,7 +18746,7 @@ operation.
Semantics:
""""""""""
-The '``llvm.vp.fdiv``' intrinsic performs floating-point division (:ref:`add <i_fdiv>`)
+The '``llvm.vp.fdiv``' intrinsic performs floating-point division (:ref:`fdiv <i_fdiv>`)
of the first and second vector operand on each enabled lane. The result on
disabled lanes is undefined. The operation is performed in the default
floating-point environment.
@@ -18795,7 +18795,7 @@ operation.
Semantics:
""""""""""
-The '``llvm.vp.frem``' intrinsic performs floating-point remainder (:ref:`add <i_frem>`)
+The '``llvm.vp.frem``' intrinsic performs floating-point remainder (:ref:`frem <i_frem>`)
of the first and second vector operand on each enabled lane. The result on
disabled lanes is undefined. The operation is performed in the default
floating-point environment.
@@ -18812,6 +18812,54 @@ Examples:
%also.r = select <4 x i1> %mask, <4 x float> %t, <4 x float> undef
+.. _int_vp_fneg:
+
+'``llvm.vp.fneg.*``' Intrinsics
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Syntax:
+"""""""
+This is an overloaded intrinsic.
+
+::
+
+ declare <16 x float> @llvm.vp.fneg.v16f32 (<16 x float> <op>, <16 x i1> <mask>, i32 <vector_length>)
+ declare <vscale x 4 x float> @llvm.vp.fneg.nxv4f32 (<vscale x 4 x float> <op>, <vscale x 4 x i1> <mask>, i32 <vector_length>)
+ declare <256 x double> @llvm.vp.fneg.v256f64 (<256 x double> <op>, <256 x i1> <mask>, i32 <vector_length>)
+
+Overview:
+"""""""""
+
+Predicated floating-point negation of a vector of floating-point values.
+
+
+Arguments:
+""""""""""
+
+The first operand and the result have the same vector of floating-point type.
+The second operand is the vector mask and has the same number of elements as the
+result vector type. The third operand is the explicit vector length of the
+operation.
+
+Semantics:
+""""""""""
+
+The '``llvm.vp.fneg``' intrinsic performs floating-point negation (:ref:`fneg <i_fneg>`)
+of the first vector operand on each enabled lane. The result on disabled lanes
+is undefined.
+
+Examples:
+"""""""""
+
+.. code-block:: llvm
+
+ %r = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %a, <4 x i1> %mask, i32 %evl)
+ ;; For all lanes below %evl, %r is lane-wise equivalent to %also.r
+
+ %t = fneg <4 x float> %a
+ %also.r = select <4 x i1> %mask, <4 x float> %t, <4 x float> undef
+
+
.. _int_vp_fma:
'``llvm.vp.fma.*``' Intrinsics
diff --git a/llvm/include/llvm/IR/Intrinsics.td b/llvm/include/llvm/IR/Intrinsics.td
index 2a5d8dce238a3..e7d38276f35e5 100644
--- a/llvm/include/llvm/IR/Intrinsics.td
+++ b/llvm/include/llvm/IR/Intrinsics.td
@@ -1505,6 +1505,11 @@ let IntrProperties =
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
llvm_i32_ty]>;
+ def int_vp_fneg : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
+ [ LLVMMatchType<0>,
+ LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
+ llvm_i32_ty]>;
+
def int_vp_fma : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ],
[ LLVMMatchType<0>,
LLVMMatchType<0>,
diff --git a/llvm/include/llvm/IR/VPIntrinsics.def b/llvm/include/llvm/IR/VPIntrinsics.def
index c57486ef1b6ec..4d75e1c37a1cd 100644
--- a/llvm/include/llvm/IR/VPIntrinsics.def
+++ b/llvm/include/llvm/IR/VPIntrinsics.def
@@ -211,6 +211,11 @@ HELPER_REGISTER_BINARY_FP_VP(frem, VP_FREM, FRem)
#undef HELPER_REGISTER_BINARY_FP_VP
+// llvm.vp.fneg(x,mask,vlen)
+BEGIN_REGISTER_VP(vp_fneg, 1, 2, VP_FNEG, -1)
+VP_PROPERTY_FUNCTIONAL_OPC(FNeg)
+END_REGISTER_VP(vp_fneg, VP_FNEG)
+
// llvm.vp.fma(x,y,z,mask,vlen)
BEGIN_REGISTER_VP(vp_fma, 3, 4, VP_FMA, -1)
VP_PROPERTY_CONSTRAINEDFP(1, 1, experimental_constrained_fma)
diff --git a/llvm/unittests/IR/VPIntrinsicTest.cpp b/llvm/unittests/IR/VPIntrinsicTest.cpp
index 440b121d63146..952b6f2b0e4b1 100644
--- a/llvm/unittests/IR/VPIntrinsicTest.cpp
+++ b/llvm/unittests/IR/VPIntrinsicTest.cpp
@@ -51,8 +51,10 @@ class VPIntrinsicTest : public testing::Test {
Str << " declare <8 x float> @llvm.vp." << BinaryFPOpcode
<< ".v8f32(<8 x float>, <8 x float>, <8 x i1>, i32) ";
+ Str << " declare <8 x float> @llvm.vp.fneg.v8f32(<8 x float>, <8 x i1>, "
+ "i32)";
Str << " declare <8 x float> @llvm.vp.fma.v8f32(<8 x float>, <8 x float>, "
- "<8 x float>, <8 x i1>, i32) ";
+ "<8 x float>, <8 x i1>, i32) ";
Str << " declare void @llvm.vp.store.v8i32.p0v8i32(<8 x i32>, <8 x i32>*, "
"<8 x i1>, i32) ";
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