[llvm] 3fc40b6 - X86: gate all vmovsh instructions on FP16 support.
Tim Northover via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 9 04:29:22 PST 2022
Author: Tim Northover
Date: 2022-02-09T12:29:16Z
New Revision: 3fc40b6e6628cd3206d5aaf2bfb864add7d74fe1
URL: https://github.com/llvm/llvm-project/commit/3fc40b6e6628cd3206d5aaf2bfb864add7d74fe1
DIFF: https://github.com/llvm/llvm-project/commit/3fc40b6e6628cd3206d5aaf2bfb864add7d74fe1.diff
LOG: X86: gate all vmovsh instructions on FP16 support.
Previously the `let Predicates = ...` line only applied to the rr version, and
so VMOVSH was being emitted whenever HasAVX512 (the default) applied. This is
not right.
Added:
Modified:
llvm/lib/Target/X86/X86InstrAVX512.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td
index bc67d1f89d7f7..09e854d1ca61d 100644
--- a/llvm/lib/Target/X86/X86InstrAVX512.td
+++ b/llvm/lib/Target/X86/X86InstrAVX512.td
@@ -4100,13 +4100,15 @@ def : Pat<(f64 (bitconvert VK64:$src)),
multiclass avx512_move_scalar<string asm, SDNode OpNode, PatFrag vzload_frag,
X86VectorVTInfo _,
- list<Predicate> prd = [HasAVX512, OptForSize]> {
- let Predicates = prd in
+ list<Predicate> prd = [HasAVX512],
+ list<Predicate> prdsize = [HasAVX512, OptForSize]> {
+ let Predicates = prdsize in
def rr : AVX512PI<0x10, MRMSrcReg, (outs _.RC:$dst),
(ins _.RC:$src1, _.RC:$src2),
!strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
[(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, _.RC:$src2)))],
_.ExeDomain>, EVEX_4V, Sched<[SchedWriteFShuffle.XMM]>;
+ let Predicates = prd in {
def rrkz : AVX512PI<0x10, MRMSrcReg, (outs _.RC:$dst),
(ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
!strconcat(asm, "\t{$src2, $src1, $dst {${mask}} {z}|",
@@ -4159,6 +4161,7 @@ multiclass avx512_move_scalar<string asm, SDNode OpNode, PatFrag vzload_frag,
!strconcat(asm, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
[], _.ExeDomain>, EVEX, EVEX_K, Sched<[WriteFStore]>,
NotMemoryFoldable;
+ } // Predicates
}
defm VMOVSSZ : avx512_move_scalar<"vmovss", X86Movss, X86vzload32, f32x_info>,
@@ -4168,7 +4171,7 @@ defm VMOVSDZ : avx512_move_scalar<"vmovsd", X86Movsd, X86vzload64, f64x_info>,
VEX_LIG, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
defm VMOVSHZ : avx512_move_scalar<"vmovsh", X86Movsh, X86vzload16, f16x_info,
- [HasFP16]>,
+ [HasFP16], [HasFP16]>,
VEX_LIG, T_MAP5XS, EVEX_CD8<16, CD8VT1>;
multiclass avx512_move_scalar_lowering<string InstrStr, SDNode OpNode,
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