[PATCH] D119252: [AArch64][SVE] Fix selection failure during lowering of shuffle_vector

[Bradley Smith via Phabricator via llvm-commits]

bsmith updated this revision to Diff 407119.
bsmith added a comment.

- Tighten type size check
- Move test to already existing file
- Add rudimentary check lines to test


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D119252/new/

https://reviews.llvm.org/D119252

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll


Index: llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll
===================================================================
--- llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll
+++ llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll
@@ -1,4 +1,4 @@
-; RUN: llc -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s
+; RUN: llc < %s | FileCheck %s
 
 target triple = "aarch64-unknown-linux-gnu"
 
@@ -14,4 +14,22 @@
   ret void
 }
 
-attributes #0 = { nounwind "target-features"="+sve" }
+; Ensure we don't crash when trying to lower a shuffle via and extract
+define void @crash_when_lowering_extract_shuffle(<32 x i32>* %dst, i1 %cond) #0 {
+; CHECK-LABEL: crash_when_lowering_extract_shuffle:
+; CHECK:       ld1w { z3.s }, p0/z, [x0]
+; CHECK:       st1w { z3.s }, p0, [x0]
+  %broadcast.splat = shufflevector <32 x i1> zeroinitializer, <32 x i1> zeroinitializer, <32 x i32> zeroinitializer
+  br i1 %cond, label %exit, label %vector.body
+
+vector.body:
+  %1 = load <32 x i32>, <32 x i32>* %dst, align 16
+  %predphi = select <32 x i1> %broadcast.splat, <32 x i32> zeroinitializer, <32 x i32> %1
+  store <32 x i32> %predphi, <32 x i32>* %dst, align 16
+  br label %exit
+
+exit:
+  ret void
+}
+
+attributes #0 = { vscale_range(2,2) "target-features"="+sve" }
Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -9728,6 +9728,10 @@
     if (ExtIdxInBits % CastedEltBitWidth != 0)
       return false;
 
+    // Can't handle cases where vector size is not 128-bit
+    if (!Extract.getOperand(0).getValueType().is128BitVector())
+      return false;
+
     // Update the lane value by offsetting with the scaled extract index.
     LaneC += ExtIdxInBits / CastedEltBitWidth;
 


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