[PATCH] D119105: [DAGCombiner][AArch64] Enhance to fold CSNEG into CSINC instruction

[Allen zhong via Phabricator via llvm-commits]

Allen added a comment.

In D119105#3304447 <https://reviews.llvm.org/D119105#3304447>, @dmgreen wrote:

> The code is very similar to the performAddCSelIntoCSinc method. Can they share the same code, with the differences for CSNeg accounted for?

Thanks for you comment again! I has tried it before, it seems much complicated, I'll update if you think still it's better to share ?

    // The CSEL should include a const one operand, and the CSNEG should include
    // One or NegOne operand.
    ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(LHS.getOperand(0));
    ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(LHS.getOperand(1));
    if (!CTVal || !CFVal)
      return SDValue();
  
    if (!(LHS.getOpcode() == AArch64ISD::CSEL &&
          (CTVal->isOne() || CFVal->isOne())) ||
        !(LHS.getOpcode() == AArch64ISD::CSNEG &&
          (CTVal->isOne() || CFVal->isAllOnes())))
      return SDValue();
  
    // Switch CSEL(1, c, cc) to CSEL(c, 1, !cc)
    if (LHS.getOpcode() == AArch64ISD::CSEL &&
        CTVal->isOne() && !CFVal->isOne()) {
      std::swap(CTVal, CFVal);
      AArch64CC = AArch64CC::getInvertedCondCode(AArch64CC);
    }
  
    SDLoc DL(N);
    // Switch CSNEG(1, c, cc) to CSNEG(-c, -1, !cc)
    if (LHS.getOpcode() == AArch64ISD::CSNEG &&
      CTVal->isOne() && !CFVal->isAllOnes()) {
      int64_t C = -1 * CFVal->getSExtValue();
      CTVal = cast<ConstantSDNode>(DAG.getConstant(C, DL, VT));
      CFVal = cast<ConstantSDNode>(DAG.getConstant(-1, DL, VT));
      AArch64CC = AArch64CC::getInvertedCondCode(AArch64CC);
    }
  
  ...
  
    assert((LHS.getOpcode() == AArch64ISD::CSEL && CFVal->isOne() ||
            LHS.getOpcode() == AArch64ISD::CSNEG && CFVal->isAllOnes()) &&
           "Unexpected constant value");


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