[PATCH] D119303: [RISCV] Lower VECTOR_SPLICE to RVV instructions.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: frasercrmck, rogfer01, npanchen, ABataev, arcbbb.
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This lowers VECTOR_SPLICE to a slidedown follow by a slideup.

I've used a tail agnostic slidedown and limited the VL to only the
elements that will not be overwritten by the slideup. The slideup
uses VLMax for its VL. It unfortunately uses tail undisturbed policy
but it isn't required as there is no tail. We just need the merge
operand to carry the bits for the lower portion of the result.

Care was taken to ensure that either the slideup or slidedown will
be able to use a .vi instruction when the immediate is small. Which
one uses the immediate depends on the sign of the immediate.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D119303

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/test/CodeGen/RISCV/rvv/vector-splice.ll

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