[llvm] 2af4a55 - GlobalISel: Constant fold FP bin ops in MIRBuilder
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 8 16:01:25 PST 2022
Author: Matt Arsenault
Date: 2022-02-08T18:51:10-05:00
New Revision: 2af4a554fedbd3a2d58b993f8fceeb1bce565d08
URL: https://github.com/llvm/llvm-project/commit/2af4a554fedbd3a2d58b993f8fceeb1bce565d08
DIFF: https://github.com/llvm/llvm-project/commit/2af4a554fedbd3a2d58b993f8fceeb1bce565d08.diff
LOG: GlobalISel: Constant fold FP bin ops in MIRBuilder
Might as well handle these if we're going to handle the integer ops
here.
Added:
Modified:
llvm/lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp
llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fold-binop-into-select.mir
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp
index 33f03f5d6ec5..4b136f18ba98 100644
--- a/llvm/lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp
@@ -206,6 +206,26 @@ MachineInstrBuilder CSEMIRBuilder::buildInstr(unsigned Opc,
return buildConstant(DstOps[0], *Cst);
break;
}
+ case TargetOpcode::G_FADD:
+ case TargetOpcode::G_FSUB:
+ case TargetOpcode::G_FMUL:
+ case TargetOpcode::G_FDIV:
+ case TargetOpcode::G_FREM:
+ case TargetOpcode::G_FMINNUM:
+ case TargetOpcode::G_FMAXNUM:
+ case TargetOpcode::G_FMINNUM_IEEE:
+ case TargetOpcode::G_FMAXNUM_IEEE:
+ case TargetOpcode::G_FMINIMUM:
+ case TargetOpcode::G_FMAXIMUM:
+ case TargetOpcode::G_FCOPYSIGN: {
+ // Try to constant fold these.
+ assert(SrcOps.size() == 2 && "Invalid sources");
+ assert(DstOps.size() == 1 && "Invalid dsts");
+ if (Optional<APFloat> Cst = ConstantFoldFPBinOp(
+ Opc, SrcOps[0].getReg(), SrcOps[1].getReg(), *getMRI()))
+ return buildFConstant(DstOps[0], *Cst);
+ break;
+ }
case TargetOpcode::G_SEXT_INREG: {
assert(DstOps.size() == 1 && "Invalid dst ops");
assert(SrcOps.size() == 2 && "Invalid src ops");
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fold-binop-into-select.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fold-binop-into-select.mir
index 7b3b0862308e..aceb983e1e0a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fold-binop-into-select.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fold-binop-into-select.mir
@@ -1040,12 +1040,9 @@ body: |
; CHECK-NEXT: %reg:_(s32) = COPY $vgpr0
; CHECK-NEXT: %zero:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: %cond:_(s1) = G_ICMP intpred(eq), %reg(s32), %zero
- ; CHECK-NEXT: %two:_(s32) = G_FCONSTANT float 2.000000e+00
- ; CHECK-NEXT: %four:_(s32) = G_FCONSTANT float 4.000000e+00
- ; CHECK-NEXT: %sixteen:_(s32) = G_FCONSTANT float 1.600000e+01
- ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD %two, %sixteen
- ; CHECK-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD %four, %sixteen
- ; CHECK-NEXT: %fadd:_(s32) = nnan G_SELECT %cond(s1), [[FADD]], [[FADD1]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.800000e+01
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 2.000000e+01
+ ; CHECK-NEXT: %fadd:_(s32) = nnan G_SELECT %cond(s1), [[C]], [[C1]]
; CHECK-NEXT: S_ENDPGM 0, implicit %fadd(s32)
%reg:_(s32) = COPY $vgpr0
%zero:_(s32) = G_CONSTANT i32 0
@@ -1070,12 +1067,9 @@ body: |
; CHECK-NEXT: %reg:_(s32) = COPY $vgpr0
; CHECK-NEXT: %zero:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: %cond:_(s1) = G_ICMP intpred(eq), %reg(s32), %zero
- ; CHECK-NEXT: %two:_(s32) = G_FCONSTANT float 2.000000e+00
- ; CHECK-NEXT: %four:_(s32) = G_FCONSTANT float 4.000000e+00
- ; CHECK-NEXT: %sixteen:_(s32) = G_FCONSTANT float 1.600000e+01
- ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD %sixteen, %two
- ; CHECK-NEXT: [[FADD1:%[0-9]+]]:_(s32) = G_FADD %sixteen, %four
- ; CHECK-NEXT: %fadd:_(s32) = nnan G_SELECT %cond(s1), [[FADD]], [[FADD1]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.800000e+01
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 2.000000e+01
+ ; CHECK-NEXT: %fadd:_(s32) = nnan G_SELECT %cond(s1), [[C]], [[C1]]
; CHECK-NEXT: S_ENDPGM 0, implicit %fadd(s32)
%reg:_(s32) = COPY $vgpr0
%zero:_(s32) = G_CONSTANT i32 0
@@ -1100,12 +1094,9 @@ body: |
; CHECK-NEXT: %reg:_(s32) = COPY $vgpr0
; CHECK-NEXT: %zero:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: %cond:_(s1) = G_ICMP intpred(eq), %reg(s32), %zero
- ; CHECK-NEXT: %two:_(s32) = G_FCONSTANT float 2.000000e+00
- ; CHECK-NEXT: %four:_(s32) = G_FCONSTANT float 4.000000e+00
- ; CHECK-NEXT: %sixteen:_(s32) = G_FCONSTANT float 1.600000e+01
- ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB %two, %sixteen
- ; CHECK-NEXT: [[FSUB1:%[0-9]+]]:_(s32) = G_FSUB %four, %sixteen
- ; CHECK-NEXT: %fsub:_(s32) = nnan G_SELECT %cond(s1), [[FSUB]], [[FSUB1]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float -1.400000e+01
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float -1.200000e+01
+ ; CHECK-NEXT: %fsub:_(s32) = nnan G_SELECT %cond(s1), [[C]], [[C1]]
; CHECK-NEXT: S_ENDPGM 0, implicit %fsub(s32)
%reg:_(s32) = COPY $vgpr0
%zero:_(s32) = G_CONSTANT i32 0
@@ -1130,12 +1121,9 @@ body: |
; CHECK-NEXT: %reg:_(s32) = COPY $vgpr0
; CHECK-NEXT: %zero:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: %cond:_(s1) = G_ICMP intpred(eq), %reg(s32), %zero
- ; CHECK-NEXT: %two:_(s32) = G_FCONSTANT float 2.000000e+00
- ; CHECK-NEXT: %four:_(s32) = G_FCONSTANT float 4.000000e+00
- ; CHECK-NEXT: %sixteen:_(s32) = G_FCONSTANT float 1.600000e+01
- ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL %two, %sixteen
- ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL %four, %sixteen
- ; CHECK-NEXT: %fmul:_(s32) = nnan G_SELECT %cond(s1), [[FMUL]], [[FMUL1]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 3.200000e+01
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 6.400000e+01
+ ; CHECK-NEXT: %fmul:_(s32) = nnan G_SELECT %cond(s1), [[C]], [[C1]]
; CHECK-NEXT: S_ENDPGM 0, implicit %fmul(s32)
%reg:_(s32) = COPY $vgpr0
%zero:_(s32) = G_CONSTANT i32 0
@@ -1160,12 +1148,9 @@ body: |
; CHECK-NEXT: %reg:_(s32) = COPY $vgpr0
; CHECK-NEXT: %zero:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: %cond:_(s1) = G_ICMP intpred(eq), %reg(s32), %zero
- ; CHECK-NEXT: %two:_(s32) = G_FCONSTANT float 2.000000e+00
- ; CHECK-NEXT: %four:_(s32) = G_FCONSTANT float 4.000000e+00
- ; CHECK-NEXT: %sixteen:_(s32) = G_FCONSTANT float 1.600000e+01
- ; CHECK-NEXT: [[FDIV:%[0-9]+]]:_(s32) = G_FDIV %two, %sixteen
- ; CHECK-NEXT: [[FDIV1:%[0-9]+]]:_(s32) = G_FDIV %four, %sixteen
- ; CHECK-NEXT: %fdiv:_(s32) = nnan G_SELECT %cond(s1), [[FDIV]], [[FDIV1]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.250000e-01
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 2.500000e-01
+ ; CHECK-NEXT: %fdiv:_(s32) = nnan G_SELECT %cond(s1), [[C]], [[C1]]
; CHECK-NEXT: S_ENDPGM 0, implicit %fdiv(s32)
%reg:_(s32) = COPY $vgpr0
%zero:_(s32) = G_CONSTANT i32 0
@@ -1192,10 +1177,7 @@ body: |
; CHECK-NEXT: %cond:_(s1) = G_ICMP intpred(eq), %reg(s32), %zero
; CHECK-NEXT: %two:_(s32) = G_FCONSTANT float 2.000000e+00
; CHECK-NEXT: %four:_(s32) = G_FCONSTANT float 4.000000e+00
- ; CHECK-NEXT: %sixteen:_(s32) = G_FCONSTANT float 1.600000e+01
- ; CHECK-NEXT: [[FREM:%[0-9]+]]:_(s32) = G_FREM %two, %sixteen
- ; CHECK-NEXT: [[FREM1:%[0-9]+]]:_(s32) = G_FREM %four, %sixteen
- ; CHECK-NEXT: %frem:_(s32) = nnan G_SELECT %cond(s1), [[FREM]], [[FREM1]]
+ ; CHECK-NEXT: %frem:_(s32) = nnan G_SELECT %cond(s1), %two, %four
; CHECK-NEXT: S_ENDPGM 0, implicit %frem(s32)
%reg:_(s32) = COPY $vgpr0
%zero:_(s32) = G_CONSTANT i32 0
@@ -1251,10 +1233,7 @@ body: |
; CHECK-NEXT: %cond:_(s1) = G_ICMP intpred(eq), %reg(s32), %zero
; CHECK-NEXT: %two:_(s32) = G_FCONSTANT float 2.000000e+00
; CHECK-NEXT: %four:_(s32) = G_FCONSTANT float 4.000000e+00
- ; CHECK-NEXT: %sixteen:_(s32) = G_FCONSTANT float 1.600000e+01
- ; CHECK-NEXT: [[FMINNUM:%[0-9]+]]:_(s32) = G_FMINNUM %two, %sixteen
- ; CHECK-NEXT: [[FMINNUM1:%[0-9]+]]:_(s32) = G_FMINNUM %four, %sixteen
- ; CHECK-NEXT: %fminnum:_(s32) = nnan G_SELECT %cond(s1), [[FMINNUM]], [[FMINNUM1]]
+ ; CHECK-NEXT: %fminnum:_(s32) = nnan G_SELECT %cond(s1), %two, %four
; CHECK-NEXT: S_ENDPGM 0, implicit %fminnum(s32)
%reg:_(s32) = COPY $vgpr0
%zero:_(s32) = G_CONSTANT i32 0
@@ -1308,12 +1287,9 @@ body: |
; CHECK-NEXT: %reg:_(s32) = COPY $vgpr0
; CHECK-NEXT: %zero:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: %cond:_(s1) = G_ICMP intpred(eq), %reg(s32), %zero
- ; CHECK-NEXT: %two:_(s32) = G_FCONSTANT float 2.000000e+00
; CHECK-NEXT: %four:_(s32) = G_FCONSTANT float 4.000000e+00
; CHECK-NEXT: %three:_(s32) = G_FCONSTANT float 3.000000e+00
- ; CHECK-NEXT: [[FMAXNUM:%[0-9]+]]:_(s32) = G_FMAXNUM %two, %three
- ; CHECK-NEXT: [[FMAXNUM1:%[0-9]+]]:_(s32) = G_FMAXNUM %four, %three
- ; CHECK-NEXT: %fmaxnum:_(s32) = nnan G_SELECT %cond(s1), [[FMAXNUM]], [[FMAXNUM1]]
+ ; CHECK-NEXT: %fmaxnum:_(s32) = nnan G_SELECT %cond(s1), %three, %four
; CHECK-NEXT: S_ENDPGM 0, implicit %fmaxnum(s32)
%reg:_(s32) = COPY $vgpr0
%zero:_(s32) = G_CONSTANT i32 0
@@ -1369,10 +1345,7 @@ body: |
; CHECK-NEXT: %cond:_(s1) = G_ICMP intpred(eq), %reg(s32), %zero
; CHECK-NEXT: %two:_(s32) = G_FCONSTANT float 2.000000e+00
; CHECK-NEXT: %four:_(s32) = G_FCONSTANT float 4.000000e+00
- ; CHECK-NEXT: %sixteen:_(s32) = G_FCONSTANT float 1.600000e+01
- ; CHECK-NEXT: [[FMINIMUM:%[0-9]+]]:_(s32) = G_FMINIMUM %two, %sixteen
- ; CHECK-NEXT: [[FMINIMUM1:%[0-9]+]]:_(s32) = G_FMINIMUM %four, %sixteen
- ; CHECK-NEXT: %fminimum:_(s32) = nnan G_SELECT %cond(s1), [[FMINIMUM]], [[FMINIMUM1]]
+ ; CHECK-NEXT: %fminimum:_(s32) = nnan G_SELECT %cond(s1), %two, %four
; CHECK-NEXT: S_ENDPGM 0, implicit %fminimum(s32)
%reg:_(s32) = COPY $vgpr0
%zero:_(s32) = G_CONSTANT i32 0
@@ -1397,12 +1370,9 @@ body: |
; CHECK-NEXT: %reg:_(s32) = COPY $vgpr0
; CHECK-NEXT: %zero:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: %cond:_(s1) = G_ICMP intpred(eq), %reg(s32), %zero
- ; CHECK-NEXT: %two:_(s32) = G_FCONSTANT float 2.000000e+00
; CHECK-NEXT: %four:_(s32) = G_FCONSTANT float 4.000000e+00
; CHECK-NEXT: %three:_(s32) = G_FCONSTANT float 3.000000e+00
- ; CHECK-NEXT: [[FMAXIMUM:%[0-9]+]]:_(s32) = G_FMAXIMUM %two, %three
- ; CHECK-NEXT: [[FMAXIMUM1:%[0-9]+]]:_(s32) = G_FMAXIMUM %four, %three
- ; CHECK-NEXT: %fmaximum:_(s32) = nnan G_SELECT %cond(s1), [[FMAXIMUM]], [[FMAXIMUM1]]
+ ; CHECK-NEXT: %fmaximum:_(s32) = nnan G_SELECT %cond(s1), %three, %four
; CHECK-NEXT: S_ENDPGM 0, implicit %fmaximum(s32)
%reg:_(s32) = COPY $vgpr0
%zero:_(s32) = G_CONSTANT i32 0
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