[llvm] 930f249 - GlobalISel: Constant fold integer min/max opcodes

[Matt Arsenault via llvm-commits]

Author: Matt Arsenault
Date: 2022-02-08T18:50:35-05:00
New Revision: 930f2498d46305c7d787354fd629bd686fbcc3a3

URL: https://github.com/llvm/llvm-project/commit/930f2498d46305c7d787354fd629bd686fbcc3a3
DIFF: https://github.com/llvm/llvm-project/commit/930f2498d46305c7d787354fd629bd686fbcc3a3.diff

LOG: GlobalISel: Constant fold integer min/max opcodes

Added: 
    

Modified: 
    llvm/lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp
    llvm/lib/CodeGen/GlobalISel/Utils.cpp
    llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fold-binop-into-select.mir

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp
index 1a642e233a6ac..33f03f5d6ec5f 100644
--- a/llvm/lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp
@@ -185,7 +185,11 @@ MachineInstrBuilder CSEMIRBuilder::buildInstr(unsigned Opc,
   case TargetOpcode::G_UDIV:
   case TargetOpcode::G_SDIV:
   case TargetOpcode::G_UREM:
-  case TargetOpcode::G_SREM: {
+  case TargetOpcode::G_SREM:
+  case TargetOpcode::G_SMIN:
+  case TargetOpcode::G_SMAX:
+  case TargetOpcode::G_UMIN:
+  case TargetOpcode::G_UMAX: {
     // Try to constant fold these.
     assert(SrcOps.size() == 2 && "Invalid sources");
     assert(DstOps.size() == 1 && "Invalid dsts");

diff  --git a/llvm/lib/CodeGen/GlobalISel/Utils.cpp b/llvm/lib/CodeGen/GlobalISel/Utils.cpp
index 6a8750478b48e..ea47190e92328 100644
--- a/llvm/lib/CodeGen/GlobalISel/Utils.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/Utils.cpp
@@ -533,6 +533,14 @@ Optional<APInt> llvm::ConstantFoldBinOp(unsigned Opcode, const Register Op1,
     if (!C2.getBoolValue())
       break;
     return C1.srem(C2);
+  case TargetOpcode::G_SMIN:
+    return APIntOps::smin(C1, C2);
+  case TargetOpcode::G_SMAX:
+    return APIntOps::smax(C1, C2);
+  case TargetOpcode::G_UMIN:
+    return APIntOps::umin(C1, C2);
+  case TargetOpcode::G_UMAX:
+    return APIntOps::umax(C1, C2);
   }
 
   return None;

diff  --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fold-binop-into-select.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fold-binop-into-select.mir
index 802e7eec17362..7b3b0862308eb 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fold-binop-into-select.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fold-binop-into-select.mir
@@ -944,10 +944,7 @@ body: |
     ; CHECK-NEXT: %cond:_(s1) = G_ICMP intpred(eq), %reg(s32), %zero
     ; CHECK-NEXT: %ten:_(s32) = G_CONSTANT i32 10
     ; CHECK-NEXT: %twenty:_(s32) = G_CONSTANT i32 20
-    ; CHECK-NEXT: %thirty:_(s32) = G_CONSTANT i32 30
-    ; CHECK-NEXT: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN %ten, %thirty
-    ; CHECK-NEXT: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN %twenty, %thirty
-    ; CHECK-NEXT: %smin:_(s32) = G_SELECT %cond(s1), [[SMIN]], [[SMIN1]]
+    ; CHECK-NEXT: %smin:_(s32) = G_SELECT %cond(s1), %ten, %twenty
     ; CHECK-NEXT: S_ENDPGM 0, implicit %smin(s32)
     %reg:_(s32) = COPY $vgpr0
     %zero:_(s32) = G_CONSTANT i32 0
@@ -969,16 +966,8 @@ body: |
     ; CHECK-LABEL: name: fold_smax_into_select_s32_0
     ; CHECK: liveins: $vgpr0
     ; CHECK-NEXT: {{  $}}
-    ; CHECK-NEXT: %reg:_(s32) = COPY $vgpr0
-    ; CHECK-NEXT: %zero:_(s32) = G_CONSTANT i32 0
-    ; CHECK-NEXT: %cond:_(s1) = G_ICMP intpred(eq), %reg(s32), %zero
-    ; CHECK-NEXT: %ten:_(s32) = G_CONSTANT i32 10
-    ; CHECK-NEXT: %twenty:_(s32) = G_CONSTANT i32 20
     ; CHECK-NEXT: %thirty:_(s32) = G_CONSTANT i32 30
-    ; CHECK-NEXT: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX %ten, %thirty
-    ; CHECK-NEXT: [[SMAX1:%[0-9]+]]:_(s32) = G_SMAX %twenty, %thirty
-    ; CHECK-NEXT: %smax:_(s32) = G_SELECT %cond(s1), [[SMAX]], [[SMAX1]]
-    ; CHECK-NEXT: S_ENDPGM 0, implicit %smax(s32)
+    ; CHECK-NEXT: S_ENDPGM 0, implicit %thirty(s32)
     %reg:_(s32) = COPY $vgpr0
     %zero:_(s32) = G_CONSTANT i32 0
     %cond:_(s1) = G_ICMP intpred(eq), %reg, %zero
@@ -1004,10 +993,7 @@ body: |
     ; CHECK-NEXT: %cond:_(s1) = G_ICMP intpred(eq), %reg(s32), %zero
     ; CHECK-NEXT: %ten:_(s32) = G_CONSTANT i32 10
     ; CHECK-NEXT: %twenty:_(s32) = G_CONSTANT i32 20
-    ; CHECK-NEXT: %thirty:_(s32) = G_CONSTANT i32 30
-    ; CHECK-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN %ten, %thirty
-    ; CHECK-NEXT: [[UMIN1:%[0-9]+]]:_(s32) = G_UMIN %twenty, %thirty
-    ; CHECK-NEXT: %umin:_(s32) = G_SELECT %cond(s1), [[UMIN]], [[UMIN1]]
+    ; CHECK-NEXT: %umin:_(s32) = G_SELECT %cond(s1), %ten, %twenty
     ; CHECK-NEXT: S_ENDPGM 0, implicit %umin(s32)
     %reg:_(s32) = COPY $vgpr0
     %zero:_(s32) = G_CONSTANT i32 0
@@ -1029,16 +1015,8 @@ body: |
     ; CHECK-LABEL: name: fold_umax_into_select_s32_0
     ; CHECK: liveins: $vgpr0
     ; CHECK-NEXT: {{  $}}
-    ; CHECK-NEXT: %reg:_(s32) = COPY $vgpr0
-    ; CHECK-NEXT: %zero:_(s32) = G_CONSTANT i32 0
-    ; CHECK-NEXT: %cond:_(s1) = G_ICMP intpred(eq), %reg(s32), %zero
-    ; CHECK-NEXT: %ten:_(s32) = G_CONSTANT i32 10
-    ; CHECK-NEXT: %twenty:_(s32) = G_CONSTANT i32 20
     ; CHECK-NEXT: %thirty:_(s32) = G_CONSTANT i32 30
-    ; CHECK-NEXT: [[UMAX:%[0-9]+]]:_(s32) = G_UMAX %ten, %thirty
-    ; CHECK-NEXT: [[UMAX1:%[0-9]+]]:_(s32) = G_UMAX %twenty, %thirty
-    ; CHECK-NEXT: %umax:_(s32) = G_SELECT %cond(s1), [[UMAX]], [[UMAX1]]
-    ; CHECK-NEXT: S_ENDPGM 0, implicit %umax(s32)
+    ; CHECK-NEXT: S_ENDPGM 0, implicit %thirty(s32)
     %reg:_(s32) = COPY $vgpr0
     %zero:_(s32) = G_CONSTANT i32 0
     %cond:_(s1) = G_ICMP intpred(eq), %reg, %zero