[PATCH] D101470: [XCOFF][AIX] Peephole optimization in 32-bit TocData transformation

[Stefan Pintilie via Phabricator via llvm-commits]

stefanp added a comment.

Note that I have reviewed this patch along with https://reviews.llvm.org/D118718. The following comment applies to both patches.

There is one concern with respect to alignment. 
I've created the following test case:

  define i64 @read() {
    %1  = load i32, i32* @i1, align 1
    %2  = sext i32 %1 to i64
    ret i64 %2
  }

The assembly we create (using `llc -mtriple powerpc64-ibm-aix-xcoff test.ll`) is as follows:

  .read:
  # %bb.0:
  	lwa 3, i1[TD](2)
  	blr

The issue is that the original `ADDI` instruction is a D-Form and so no alignment is required. However, `LWA` is DS form and if the alignment for `i1` is not a multiple of 4 then the linker won't have a way to fill in that value.



================
Comment at: llvm/test/CodeGen/PowerPC/toc-data-const.ll:4
+
+; RUN llc -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck %s --check-prefix=CHECK,OPT
+; RUN: llc -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck %s --check-prefixes=CHECK,NOOPT
----------------
nit:
Forgot the `:` after the `RUN`. 


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D101470/new/

https://reviews.llvm.org/D101470