[PATCH] D116735: [RISCV] Adjust RISCV data layout by using n32:64 in layout string

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

In D116735#3247378 <https://reviews.llvm.org/D116735#3247378>, @joshua-arch1 wrote:

> In D116735#3238854 <https://reviews.llvm.org/D116735#3238854>, @craig.topper wrote:
>
>> In D116735#3230281 <https://reviews.llvm.org/D116735#3230281>, @joshua-arch1 wrote:
>>
>>> I have checked all the benchmarks. 
>>> For coremark, spec2006_int-471.omnetpp and eembc_networking_pktflow, the performance can improve by more than 3%, without degression of other cases.
>>
>> Can you say more about what hardware and ISA extensions were used for that testing?
>
> I used T-HEAD XuanTie C906 processor based on the RV64GCV instruction set and THEAD instruction extension.

Was it tested using a version of LLVM that supports the THEAD instruction extension or just the public LLVM?


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