[PATCH] D119252: [AArch64][SVE] Fix selection failure during lowering of shuffle_vector

[Bradley Smith via Phabricator via llvm-commits]

bsmith created this revision.
bsmith added reviewers: peterwaller-arm, paulwalker-arm, sdesmalen.
Herald added subscribers: psnobl, hiraditya, kristof.beyls, tschuett.
Herald added a reviewer: efriedma.
bsmith requested review of this revision.
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The lowering code for shuffle_vector has a code path that looks through
extract_subvector, this code path did not properly account for the
potential presense of larger than Neon vector types and could produce
unselectable DAG nodes.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D119252

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/sve-shuffle-crash.ll


Index: llvm/test/CodeGen/AArch64/sve-shuffle-crash.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AArch64/sve-shuffle-crash.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s
+
+target triple = "aarch64-unknown-linux-gnu"
+
+define void @foo(<32 x i32>* %dst, i1 %cond) #0 {
+  %broadcast.splat = shufflevector <32 x i1> zeroinitializer, <32 x i1> zeroinitializer, <32 x i32> zeroinitializer
+  br i1 %cond, label %exit, label %vector.body
+
+vector.body:
+  %1 = load <32 x i32>, <32 x i32>* %dst, align 16
+  %predphi = select <32 x i1> %broadcast.splat, <32 x i32> zeroinitializer, <32 x i32> %1
+  store <32 x i32> %predphi, <32 x i32>* %dst, align 16
+  br label %exit
+
+exit:
+  ret void
+}
+
+attributes #0 = { vscale_range(2,2) "target-features"="+sve" }
Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -9728,6 +9728,10 @@
     if (ExtIdxInBits % CastedEltBitWidth != 0)
       return false;
 
+    // Can't handle cases where vector size is greater than 128-bit
+    if (Extract.getOperand(0).getValueSizeInBits() > 128)
+      return false;
+
     // Update the lane value by offsetting with the scaled extract index.
     LaneC += ExtIdxInBits / CastedEltBitWidth;
 


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