[PATCH] D116877: [GlobalISel] Add big endian support in CallLowering

[Simon Pilgrim via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG76c83e747f28: [GlobalISel] Add big endian support in CallLowering (authored by 0x59616e, committed by RKSimon).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D116877/new/

https://reviews.llvm.org/D116877

Files:
  llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
  llvm/test/CodeGen/M68k/GlobalISel/irtranslator-ret.ll


Index: llvm/test/CodeGen/M68k/GlobalISel/irtranslator-ret.ll
===================================================================
--- llvm/test/CodeGen/M68k/GlobalISel/irtranslator-ret.ll
+++ llvm/test/CodeGen/M68k/GlobalISel/irtranslator-ret.ll
@@ -206,8 +206,8 @@
   ; CHECK:   [[G_LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I2]](p0)
   ; CHECK:   [[G_MERGE_VAL:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[G_LOAD1]](s32), [[G_LOAD2]](s32)
   ; CHECK:   [[G_UNMERGE_VAL1:%[0-9]+]]:_(s32), [[G_UNMERGE_VAL2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[G_MERGE_VAL]](s64)
-  ; CHECK:   $d0 = COPY [[G_UNMERGE_VAL1]](s32)
-  ; CHECK:   $d1 = COPY [[G_UNMERGE_VAL2]](s32)
-  ; CHECK:   RTS implicit $d0, implicit $d1
+  ; CHECK:   $d1 = COPY [[G_UNMERGE_VAL1]](s32)
+  ; CHECK:   $d0 = COPY [[G_UNMERGE_VAL2]](s32)
+  ; CHECK:   RTS implicit $d1, implicit $d0
   ret i64 %a
 }
Index: llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
===================================================================
--- llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
+++ llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
@@ -698,10 +698,12 @@
                       ValTy, extendOpFromFlags(Args[i].Flags[0]));
     }
 
+    bool BigEndianPartOrdering = TLI->hasBigEndianPartOrdering(OrigVT, DL);
     for (unsigned Part = 0; Part < NumParts; ++Part) {
       Register ArgReg = Args[i].Regs[Part];
       // There should be Regs.size() ArgLocs per argument.
-      VA = ArgLocs[j + Part];
+      unsigned Idx = BigEndianPartOrdering ? NumParts - 1 - Part : Part;
+      CCValAssign &VA = ArgLocs[j + Idx];
       const ISD::ArgFlagsTy Flags = Args[i].Flags[Part];
 
       if (VA.isMemLoc() && !Flags.isByVal()) {


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