[llvm] 76c83e7 - [GlobalISel] Add big endian support in CallLowering

[Simon Pilgrim via llvm-commits]

Author: Sheng
Date: 2022-02-08T14:43:38Z
New Revision: 76c83e747f28db2c4746bdb02b6728514142c732

URL: https://github.com/llvm/llvm-project/commit/76c83e747f28db2c4746bdb02b6728514142c732
DIFF: https://github.com/llvm/llvm-project/commit/76c83e747f28db2c4746bdb02b6728514142c732.diff

LOG: [GlobalISel] Add big endian support in CallLowering

When splitting values, CallLowering assumes Lo part goes first. But in big endian ISA such as M68k, Hi part goes first.

This patch fixes this.

Differential Revision: https://reviews.llvm.org/D116877

Added: 
    

Modified: 
    llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
    llvm/test/CodeGen/M68k/GlobalISel/irtranslator-ret.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
index 1ec7868f22345..4373786e29b81 100644
--- a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
@@ -698,10 +698,12 @@ bool CallLowering::handleAssignments(ValueHandler &Handler,
                       ValTy, extendOpFromFlags(Args[i].Flags[0]));
     }
 
+    bool BigEndianPartOrdering = TLI->hasBigEndianPartOrdering(OrigVT, DL);
     for (unsigned Part = 0; Part < NumParts; ++Part) {
       Register ArgReg = Args[i].Regs[Part];
       // There should be Regs.size() ArgLocs per argument.
-      VA = ArgLocs[j + Part];
+      unsigned Idx = BigEndianPartOrdering ? NumParts - 1 - Part : Part;
+      CCValAssign &VA = ArgLocs[j + Idx];
       const ISD::ArgFlagsTy Flags = Args[i].Flags[Part];
 
       if (VA.isMemLoc() && !Flags.isByVal()) {

diff  --git a/llvm/test/CodeGen/M68k/GlobalISel/irtranslator-ret.ll b/llvm/test/CodeGen/M68k/GlobalISel/irtranslator-ret.ll
index 2c809d3a97735..1dd2585991354 100644
--- a/llvm/test/CodeGen/M68k/GlobalISel/irtranslator-ret.ll
+++ b/llvm/test/CodeGen/M68k/GlobalISel/irtranslator-ret.ll
@@ -206,8 +206,8 @@ define i64 @test_ret3(i64 %a) {
   ; CHECK:   [[G_LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[G_F_I2]](p0)
   ; CHECK:   [[G_MERGE_VAL:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[G_LOAD1]](s32), [[G_LOAD2]](s32)
   ; CHECK:   [[G_UNMERGE_VAL1:%[0-9]+]]:_(s32), [[G_UNMERGE_VAL2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[G_MERGE_VAL]](s64)
-  ; CHECK:   $d0 = COPY [[G_UNMERGE_VAL1]](s32)
-  ; CHECK:   $d1 = COPY [[G_UNMERGE_VAL2]](s32)
-  ; CHECK:   RTS implicit $d0, implicit $d1
+  ; CHECK:   $d1 = COPY [[G_UNMERGE_VAL1]](s32)
+  ; CHECK:   $d0 = COPY [[G_UNMERGE_VAL2]](s32)
+  ; CHECK:   RTS implicit $d1, implicit $d0
   ret i64 %a
 }