[PATCH] D115739: [SVE][DAGCombiner] Enable ISD::ABDS and ISD::ABDU for SVE.

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

There is potential alternative for the "Smaller than legal" Neon types in D119075 <https://reviews.llvm.org/D119075> (It's an MVE patch, but the AArch64 version I have looks very similar). I'm not sure it will handle all the types here (like i1's), but I would hope SVE could be handled in the same way, and some of the assembly will be more optimal as it will use the smaller type with a single extend. I haven't had enough time to update them since the weekend yet.

There is also D119072 <https://reviews.llvm.org/D119072>, which too is a little contentious, but it uses ComputeNumSignBits and computeKnownBits/countMinLeadingZeros for detecting the number of sign bits. (The contentious part is about it running from DemandedBits, as far as I understand, not the calls to computeKnownBits). This patch it kind of doing that but just with zext/sext, and not creating the smaller type if possible.


Repository:
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  https://reviews.llvm.org/D115739/new/

https://reviews.llvm.org/D115739