[llvm] ec642ce - [CSKY] Add CSKYDisassembler.cpp to construct objdump
Zi Xuan Wu via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 8 00:03:19 PST 2022
Author: Zi Xuan Wu
Date: 2022-02-08T16:02:59+08:00
New Revision: ec642ceebc1aacc8b16249df7734b8cf90ae2963
URL: https://github.com/llvm/llvm-project/commit/ec642ceebc1aacc8b16249df7734b8cf90ae2963
DIFF: https://github.com/llvm/llvm-project/commit/ec642ceebc1aacc8b16249df7734b8cf90ae2963.diff
LOG: [CSKY] Add CSKYDisassembler.cpp to construct objdump
CSKYDisassembler tries to disassemble register MC operand from register num for different register class, and
also handles immediate num and carry flag operand which is not encoded in instruction binary.
Also enhance the printer of instruction to accept sub-option to control the print format. Sometimes, it prefers to
print number in hex, especially when immediate number represents symbol address.
Added:
llvm/lib/Target/CSKY/Disassembler/CMakeLists.txt
llvm/lib/Target/CSKY/Disassembler/CSKYDisassembler.cpp
Modified:
llvm/lib/Target/CSKY/CMakeLists.txt
llvm/lib/Target/CSKY/CSKYRegisterInfo.td
llvm/lib/Target/CSKY/MCTargetDesc/CSKYInstPrinter.cpp
llvm/test/MC/CSKY/basic-16bit.s
llvm/test/MC/CSKY/basic.s
llvm/test/MC/CSKY/fpuv2.s
llvm/test/MC/CSKY/fpuv3.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/CSKY/CMakeLists.txt b/llvm/lib/Target/CSKY/CMakeLists.txt
index 395a28a3049aa..8af00e97fbbb3 100644
--- a/llvm/lib/Target/CSKY/CMakeLists.txt
+++ b/llvm/lib/Target/CSKY/CMakeLists.txt
@@ -7,6 +7,7 @@ tablegen(LLVM CSKYGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM CSKYGenCallingConv.inc -gen-callingconv)
tablegen(LLVM CSKYGenCompressInstEmitter.inc -gen-compress-inst-emitter)
tablegen(LLVM CSKYGenDAGISel.inc -gen-dag-isel)
+tablegen(LLVM CSKYGenDisassemblerTables.inc -gen-disassembler)
tablegen(LLVM CSKYGenInstrInfo.inc -gen-instr-info)
tablegen(LLVM CSKYGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM CSKYGenMCPseudoLowering.inc -gen-pseudo-lowering)
@@ -45,5 +46,6 @@ add_llvm_target(CSKYCodeGen
)
add_subdirectory(AsmParser)
+add_subdirectory(Disassembler)
add_subdirectory(MCTargetDesc)
add_subdirectory(TargetInfo)
diff --git a/llvm/lib/Target/CSKY/CSKYRegisterInfo.td b/llvm/lib/Target/CSKY/CSKYRegisterInfo.td
index b7f4fc17166b9..d72bf81829ec7 100644
--- a/llvm/lib/Target/CSKY/CSKYRegisterInfo.td
+++ b/llvm/lib/Target/CSKY/CSKYRegisterInfo.td
@@ -81,17 +81,21 @@ let RegAltNameIndices = [ABIRegAltName] in {
def R29 : CSKYReg<29, "r29", ["rtb"]>, DwarfRegNum<[29]>;
def R30 : CSKYReg<30, "r30", ["svbr"]>, DwarfRegNum<[30]>;
def R31 : CSKYReg<31, "r31", ["tls"]>, DwarfRegNum<[31]>;
- def C : CSKYReg<32, "cr0", ["psr"]>;
+
+ // Faked for GPRTuple
+ def R32 : CSKYReg<32, "r32", ["r32"]>, DwarfRegNum<[32]>;
+
+ def C : CSKYReg<33, "cr0", ["psr"]>;
}
def GPRTuple : RegisterTuples<
[sub32_0, sub32_32],
- [(add (sequence "R%u", 0, 30)), (add (sequence "R%u", 1, 31))],
+ [(add (sequence "R%u", 0, 31)), (add (sequence "R%u", 1, 32))],
[ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
- "r24", "r25", "r26", "r27", "r28", "r29", "r30"
+ "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
]>;
// Floating point registers
diff --git a/llvm/lib/Target/CSKY/Disassembler/CMakeLists.txt b/llvm/lib/Target/CSKY/Disassembler/CMakeLists.txt
new file mode 100644
index 0000000000000..ecef8893572b2
--- /dev/null
+++ b/llvm/lib/Target/CSKY/Disassembler/CMakeLists.txt
@@ -0,0 +1,11 @@
+add_llvm_component_library(LLVMCSKYDisassembler
+ CSKYDisassembler.cpp
+
+ LINK_COMPONENTS
+ CSKYInfo
+ MCDisassembler
+ Support
+
+ ADD_TO_COMPONENT
+ CSKY
+ )
diff --git a/llvm/lib/Target/CSKY/Disassembler/CSKYDisassembler.cpp b/llvm/lib/Target/CSKY/Disassembler/CSKYDisassembler.cpp
new file mode 100644
index 0000000000000..0b6d823456f74
--- /dev/null
+++ b/llvm/lib/Target/CSKY/Disassembler/CSKYDisassembler.cpp
@@ -0,0 +1,548 @@
+//===-- CSKYDisassembler.cpp - Disassembler for CSKY ----------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the CSKYDisassembler class.
+//
+//===----------------------------------------------------------------------===//
+
+#include "MCTargetDesc/CSKYBaseInfo.h"
+#include "MCTargetDesc/CSKYMCTargetDesc.h"
+#include "TargetInfo/CSKYTargetInfo.h"
+#include "llvm/ADT/DenseMap.h"
+#include "llvm/MC/MCContext.h"
+#include "llvm/MC/MCDisassembler/MCDisassembler.h"
+#include "llvm/MC/MCFixedLenDisassembler.h"
+#include "llvm/MC/MCInst.h"
+#include "llvm/MC/MCInstrInfo.h"
+#include "llvm/MC/MCRegisterInfo.h"
+#include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/MC/TargetRegistry.h"
+#include "llvm/Support/Endian.h"
+
+using namespace llvm;
+
+#define DEBUG_TYPE "csky-disassembler"
+
+typedef MCDisassembler::DecodeStatus DecodeStatus;
+
+namespace {
+class CSKYDisassembler : public MCDisassembler {
+ std::unique_ptr<MCInstrInfo const> const MCII;
+ mutable bool inDataRegion = false;
+ mutable StringRef symbolName;
+
+ DecodeStatus handleCROperand(MCInst &Instr) const;
+
+public:
+ CSKYDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
+ MCInstrInfo const *MCII);
+
+ DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
+ ArrayRef<uint8_t> Bytes, uint64_t Address,
+ raw_ostream &CStream) const override;
+};
+} // end anonymous namespace
+
+CSKYDisassembler::CSKYDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
+ MCInstrInfo const *MCII)
+ : MCDisassembler(STI, Ctx), MCII(MCII) {}
+
+static MCDisassembler *createCSKYDisassembler(const Target &T,
+ const MCSubtargetInfo &STI,
+ MCContext &Ctx) {
+ return new CSKYDisassembler(STI, Ctx, T.createMCInstrInfo());
+}
+
+extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeCSKYDisassembler() {
+ TargetRegistry::RegisterMCDisassembler(getTheCSKYTarget(),
+ createCSKYDisassembler);
+}
+
+static const uint16_t GPRDecoderTable[] = {
+ CSKY::R0, CSKY::R1, CSKY::R2, CSKY::R3, CSKY::R4, CSKY::R5, CSKY::R6,
+ CSKY::R7, CSKY::R8, CSKY::R9, CSKY::R10, CSKY::R11, CSKY::R12, CSKY::R13,
+ CSKY::R14, CSKY::R15, CSKY::R16, CSKY::R17, CSKY::R18, CSKY::R19, CSKY::R20,
+ CSKY::R21, CSKY::R22, CSKY::R23, CSKY::R24, CSKY::R25, CSKY::R26, CSKY::R27,
+ CSKY::R28, CSKY::R29, CSKY::R30, CSKY::R31};
+
+static const uint16_t GPRPairDecoderTable[] = {
+ CSKY::R0_R1, CSKY::R1_R2, CSKY::R2_R3, CSKY::R3_R4, CSKY::R4_R5,
+ CSKY::R5_R6, CSKY::R6_R7, CSKY::R7_R8, CSKY::R8_R9, CSKY::R9_R10,
+ CSKY::R10_R11, CSKY::R11_R12, CSKY::R12_R13, CSKY::R13_R14, CSKY::R14_R15,
+ CSKY::R15_R16, CSKY::R16_R17, CSKY::R17_R18, CSKY::R18_R19, CSKY::R19_R20,
+ CSKY::R20_R21, CSKY::R21_R22, CSKY::R22_R23, CSKY::R23_R24, CSKY::R24_R25,
+ CSKY::R25_R26, CSKY::R26_R27, CSKY::R27_R28, CSKY::R28_R29, CSKY::R29_R30,
+ CSKY::R30_R31, CSKY::R31_R32};
+
+static const uint16_t FPR32DecoderTable[] = {
+ CSKY::F0_32, CSKY::F1_32, CSKY::F2_32, CSKY::F3_32, CSKY::F4_32,
+ CSKY::F5_32, CSKY::F6_32, CSKY::F7_32, CSKY::F8_32, CSKY::F9_32,
+ CSKY::F10_32, CSKY::F11_32, CSKY::F12_32, CSKY::F13_32, CSKY::F14_32,
+ CSKY::F15_32, CSKY::F16_32, CSKY::F17_32, CSKY::F18_32, CSKY::F19_32,
+ CSKY::F20_32, CSKY::F21_32, CSKY::F22_32, CSKY::F23_32, CSKY::F24_32,
+ CSKY::F25_32, CSKY::F26_32, CSKY::F27_32, CSKY::F28_32, CSKY::F29_32,
+ CSKY::F30_32, CSKY::F31_32};
+
+static const uint16_t FPR64DecoderTable[] = {
+ CSKY::F0_64, CSKY::F1_64, CSKY::F2_64, CSKY::F3_64, CSKY::F4_64,
+ CSKY::F5_64, CSKY::F6_64, CSKY::F7_64, CSKY::F8_64, CSKY::F9_64,
+ CSKY::F10_64, CSKY::F11_64, CSKY::F12_64, CSKY::F13_64, CSKY::F14_64,
+ CSKY::F15_64, CSKY::F16_64, CSKY::F17_64, CSKY::F18_64, CSKY::F19_64,
+ CSKY::F20_64, CSKY::F21_64, CSKY::F22_64, CSKY::F23_64, CSKY::F24_64,
+ CSKY::F25_64, CSKY::F26_64, CSKY::F27_64, CSKY::F28_64, CSKY::F29_64,
+ CSKY::F30_64, CSKY::F31_64};
+
+static const uint16_t FPR128DecoderTable[] = {
+ CSKY::F0_128, CSKY::F1_128, CSKY::F2_128, CSKY::F3_128, CSKY::F4_128,
+ CSKY::F5_128, CSKY::F6_128, CSKY::F7_128, CSKY::F8_128, CSKY::F9_128,
+ CSKY::F10_128, CSKY::F11_128, CSKY::F12_128, CSKY::F13_128, CSKY::F14_128,
+ CSKY::F15_128, CSKY::F16_128, CSKY::F17_128, CSKY::F18_128, CSKY::F19_128,
+ CSKY::F20_128, CSKY::F21_128, CSKY::F22_128, CSKY::F23_128, CSKY::F24_128,
+ CSKY::F25_128, CSKY::F26_128, CSKY::F27_128, CSKY::F28_128, CSKY::F29_128,
+ CSKY::F30_128, CSKY::F31_128};
+
+static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint64_t RegNo,
+ uint64_t Address,
+ const void *Decoder) {
+ if (RegNo >= 32)
+ return MCDisassembler::Fail;
+
+ Inst.addOperand(MCOperand::createReg(GPRDecoderTable[RegNo]));
+ return MCDisassembler::Success;
+}
+
+static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, uint64_t RegNo,
+ uint64_t Address,
+ const void *Decoder) {
+ if (RegNo >= 32)
+ return MCDisassembler::Fail;
+
+ Inst.addOperand(MCOperand::createReg(FPR32DecoderTable[RegNo]));
+ return MCDisassembler::Success;
+}
+
+static DecodeStatus DecodesFPR32RegisterClass(MCInst &Inst, uint64_t RegNo,
+ uint64_t Address,
+ const void *Decoder) {
+ if (RegNo >= 16)
+ return MCDisassembler::Fail;
+
+ Inst.addOperand(MCOperand::createReg(FPR32DecoderTable[RegNo]));
+ return MCDisassembler::Success;
+}
+
+static DecodeStatus DecodesFPR64RegisterClass(MCInst &Inst, uint64_t RegNo,
+ uint64_t Address,
+ const void *Decoder) {
+ if (RegNo >= 16)
+ return MCDisassembler::Fail;
+
+ Inst.addOperand(MCOperand::createReg(FPR64DecoderTable[RegNo]));
+ return MCDisassembler::Success;
+}
+
+static DecodeStatus DecodesFPR64_VRegisterClass(MCInst &Inst, uint64_t RegNo,
+ uint64_t Address,
+ const void *Decoder) {
+ if (RegNo >= 16)
+ return MCDisassembler::Fail;
+
+ Inst.addOperand(MCOperand::createReg(FPR64DecoderTable[RegNo]));
+ return MCDisassembler::Success;
+}
+
+static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint64_t RegNo,
+ uint64_t Address,
+ const void *Decoder) {
+ if (RegNo >= 32)
+ return MCDisassembler::Fail;
+
+ Inst.addOperand(MCOperand::createReg(FPR64DecoderTable[RegNo]));
+ return MCDisassembler::Success;
+}
+
+static DecodeStatus DecodesFPR128RegisterClass(MCInst &Inst, uint64_t RegNo,
+ uint64_t Address,
+ const void *Decoder) {
+ if (RegNo >= 16)
+ return MCDisassembler::Fail;
+
+ Inst.addOperand(MCOperand::createReg(FPR128DecoderTable[RegNo]));
+ return MCDisassembler::Success;
+}
+
+static DecodeStatus DecodesGPRRegisterClass(MCInst &Inst, uint64_t RegNo,
+ uint64_t Address,
+ const void *Decoder) {
+ if (RegNo >= 16)
+ return MCDisassembler::Fail;
+
+ Inst.addOperand(MCOperand::createReg(GPRDecoderTable[RegNo]));
+ return MCDisassembler::Success;
+}
+
+static DecodeStatus DecodemGPRRegisterClass(MCInst &Inst, uint64_t RegNo,
+ uint64_t Address,
+ const void *Decoder) {
+ if (RegNo >= 8)
+ return MCDisassembler::Fail;
+
+ Inst.addOperand(MCOperand::createReg(GPRDecoderTable[RegNo]));
+ return MCDisassembler::Success;
+}
+
+static DecodeStatus DecodeGPRSPRegisterClass(MCInst &Inst, uint64_t RegNo,
+ uint64_t Address,
+ const void *Decoder) {
+ if (RegNo != 14)
+ return MCDisassembler::Fail;
+
+ Inst.addOperand(MCOperand::createReg(GPRDecoderTable[RegNo]));
+ return MCDisassembler::Success;
+}
+
+static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, uint64_t RegNo,
+ uint64_t Address,
+ const void *Decoder) {
+ const FeatureBitset &FeatureBits =
+ static_cast<const MCDisassembler *>(Decoder)
+ ->getSubtargetInfo()
+ .getFeatureBits();
+ bool hasHighReg = FeatureBits[CSKY::FeatureHighreg];
+
+ if (RegNo >= 32 || (!hasHighReg && RegNo >= 16))
+ return MCDisassembler::Fail;
+
+ Inst.addOperand(MCOperand::createReg(GPRPairDecoderTable[RegNo]));
+ return MCDisassembler::Success;
+}
+
+template <unsigned N, unsigned S>
+static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm,
+ int64_t Address, const void *Decoder) {
+ assert(isUInt<N>(Imm) && "Invalid immediate");
+ Inst.addOperand(MCOperand::createImm(Imm << S));
+ return MCDisassembler::Success;
+}
+
+template <unsigned N>
+static DecodeStatus decodeOImmOperand(MCInst &Inst, uint64_t Imm,
+ int64_t Address, const void *Decoder) {
+ assert(isUInt<N>(Imm) && "Invalid immediate");
+ Inst.addOperand(MCOperand::createImm(Imm + 1));
+ return MCDisassembler::Success;
+}
+
+static DecodeStatus decodeLRW16Imm8(MCInst &Inst, uint64_t Imm, int64_t Address,
+ const void *Decoder) {
+ assert(isUInt<8>(Imm) && "Invalid immediate");
+ if ((Imm >> 7) & 0x1) {
+ Inst.addOperand(MCOperand::createImm((Imm & 0x7F) << 2));
+ } else {
+ uint64_t V = ((Imm ^ 0xFFFFFFFF) & 0xFF);
+ Inst.addOperand(MCOperand::createImm(V << 2));
+ }
+
+ return MCDisassembler::Success;
+}
+
+static DecodeStatus decodeJMPIXImmOperand(MCInst &Inst, uint64_t Imm,
+ int64_t Address,
+ const void *Decoder) {
+ assert(isUInt<2>(Imm) && "Invalid immediate");
+
+ if (Imm == 0)
+ Inst.addOperand(MCOperand::createImm(16));
+ else if (Imm == 1)
+ Inst.addOperand(MCOperand::createImm(24));
+ else if (Imm == 2)
+ Inst.addOperand(MCOperand::createImm(32));
+ else if (Imm == 3)
+ Inst.addOperand(MCOperand::createImm(40));
+ else
+ return MCDisassembler::Fail;
+
+ return MCDisassembler::Success;
+}
+
+static DecodeStatus DecodeRegSeqOperand(MCInst &Inst, uint64_t Imm,
+ int64_t Address, const void *Decoder) {
+ assert(isUInt<10>(Imm) && "Invalid immediate");
+
+ auto Imm5 = Imm & 0x1f;
+ auto Ry = (Imm >> 5) & 0x1f;
+
+ if (DecodeGPRRegisterClass(Inst, Ry, Address, Decoder) ==
+ MCDisassembler::Fail)
+ return MCDisassembler::Fail;
+
+ Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Ry + Imm5]));
+
+ return MCDisassembler::Success;
+}
+
+static DecodeStatus DecodeRegSeqOperandF1(MCInst &Inst, uint64_t Imm,
+ int64_t Address,
+ const void *Decoder) {
+ assert(isUInt<10>(Imm) && "Invalid immediate");
+
+ auto Imm5 = Imm & 0x1f;
+ auto Ry = (Imm >> 5) & 0x1f;
+
+ if (DecodesFPR32RegisterClass(Inst, Ry, Address, Decoder) ==
+ MCDisassembler::Fail)
+ return MCDisassembler::Fail;
+
+ Inst.addOperand(MCOperand::createReg(FPR32DecoderTable[Ry + Imm5]));
+
+ return MCDisassembler::Success;
+}
+
+static DecodeStatus DecodeRegSeqOperandD1(MCInst &Inst, uint64_t Imm,
+ int64_t Address,
+ const void *Decoder) {
+ assert(isUInt<10>(Imm) && "Invalid immediate");
+
+ auto Imm5 = Imm & 0x1f;
+ auto Ry = (Imm >> 5) & 0x1f;
+
+ if (DecodesFPR64RegisterClass(Inst, Ry, Address, Decoder) ==
+ MCDisassembler::Fail)
+ return MCDisassembler::Fail;
+
+ Inst.addOperand(MCOperand::createReg(FPR64DecoderTable[Ry + Imm5]));
+
+ return MCDisassembler::Success;
+}
+
+static DecodeStatus DecodeRegSeqOperandF2(MCInst &Inst, uint64_t Imm,
+ int64_t Address,
+ const void *Decoder) {
+ assert(isUInt<10>(Imm) && "Invalid immediate");
+
+ auto Imm5 = Imm & 0x1f;
+ auto Ry = (Imm >> 5) & 0x1f;
+
+ if (DecodeFPR32RegisterClass(Inst, Ry, Address, Decoder) ==
+ MCDisassembler::Fail)
+ return MCDisassembler::Fail;
+
+ Inst.addOperand(MCOperand::createReg(FPR32DecoderTable[Ry + Imm5]));
+
+ return MCDisassembler::Success;
+}
+
+static DecodeStatus DecodeRegSeqOperandD2(MCInst &Inst, uint64_t Imm,
+ int64_t Address,
+ const void *Decoder) {
+ assert(isUInt<10>(Imm) && "Invalid immediate");
+
+ auto Imm5 = Imm & 0x1f;
+ auto Ry = (Imm >> 5) & 0x1f;
+
+ if (DecodeFPR64RegisterClass(Inst, Ry, Address, Decoder) ==
+ MCDisassembler::Fail)
+ return MCDisassembler::Fail;
+
+ Inst.addOperand(MCOperand::createReg(FPR64DecoderTable[Ry + Imm5]));
+
+ return MCDisassembler::Success;
+}
+
+static DecodeStatus decodeImmShiftOpValue(MCInst &Inst, uint64_t Imm,
+ int64_t Address,
+ const void *Decoder) {
+ Inst.addOperand(MCOperand::createImm(Log2(Imm)));
+ return MCDisassembler::Success;
+}
+
+template <unsigned N, unsigned S>
+static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm,
+ int64_t Address, const void *Decoder) {
+ assert(isUInt<N>(Imm) && "Invalid immediate");
+ // Sign-extend the number in the bottom N bits of Imm
+ Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm) << S));
+ return MCDisassembler::Success;
+}
+
+#include "CSKYGenDisassemblerTables.inc"
+
+DecodeStatus CSKYDisassembler::handleCROperand(MCInst &MI) const {
+
+ // FIXME: To query instruction info from td file or a table inc file
+ switch (MI.getOpcode()) {
+ default:
+ return MCDisassembler::Success;
+ case CSKY::LD16WSP:
+ case CSKY::ST16WSP:
+ case CSKY::ADDI16ZSP:
+ MI.insert(std::next(MI.begin()), MCOperand::createReg(CSKY::R14));
+ return MCDisassembler::Success;
+ case CSKY::ADDI16SPSP:
+ case CSKY::SUBI16SPSP:
+ MI.insert(MI.begin(), MCOperand::createReg(CSKY::R14));
+ MI.insert(MI.begin(), MCOperand::createReg(CSKY::R14));
+ return MCDisassembler::Success;
+ case CSKY::FCMPHS_S:
+ case CSKY::FCMPHS_D:
+ case CSKY::FCMPLT_S:
+ case CSKY::FCMPLT_D:
+ case CSKY::FCMPNE_S:
+ case CSKY::FCMPNE_D:
+ case CSKY::FCMPUO_S:
+ case CSKY::FCMPUO_D:
+ case CSKY::FCMPZHS_S:
+ case CSKY::FCMPZHS_D:
+ case CSKY::FCMPZLS_S:
+ case CSKY::FCMPZLS_D:
+ case CSKY::FCMPZNE_S:
+ case CSKY::FCMPZNE_D:
+ case CSKY::FCMPZUO_S:
+ case CSKY::FCMPZUO_D:
+ case CSKY::f2FCMPHS_S:
+ case CSKY::f2FCMPHS_D:
+ case CSKY::f2FCMPLT_S:
+ case CSKY::f2FCMPLT_D:
+ case CSKY::f2FCMPNE_S:
+ case CSKY::f2FCMPNE_D:
+ case CSKY::f2FCMPUO_S:
+ case CSKY::f2FCMPUO_D:
+ case CSKY::f2FCMPHSZ_S:
+ case CSKY::f2FCMPHSZ_D:
+ case CSKY::f2FCMPHZ_S:
+ case CSKY::f2FCMPHZ_D:
+ case CSKY::f2FCMPLSZ_S:
+ case CSKY::f2FCMPLSZ_D:
+ case CSKY::f2FCMPLTZ_S:
+ case CSKY::f2FCMPLTZ_D:
+ case CSKY::f2FCMPNEZ_S:
+ case CSKY::f2FCMPNEZ_D:
+ case CSKY::f2FCMPUOZ_S:
+ case CSKY::f2FCMPUOZ_D:
+
+ case CSKY::BT32:
+ case CSKY::BF32:
+ case CSKY::BT16:
+ case CSKY::BF16:
+ case CSKY::CMPNEI32:
+ case CSKY::CMPNEI16:
+ case CSKY::CMPNE32:
+ case CSKY::CMPNE16:
+ case CSKY::CMPHSI32:
+ case CSKY::CMPHSI16:
+ case CSKY::CMPHS32:
+ case CSKY::CMPHS16:
+ case CSKY::CMPLTI32:
+ case CSKY::CMPLTI16:
+ case CSKY::CMPLT32:
+ case CSKY::CMPLT16:
+ case CSKY::BTSTI32:
+ case CSKY::BTSTI16:
+ case CSKY::TSTNBZ32:
+ case CSKY::TSTNBZ16:
+ case CSKY::TST32:
+ case CSKY::TST16:
+ MI.insert(MI.begin(), MCOperand::createReg(CSKY::C));
+ return MCDisassembler::Success;
+ case CSKY::LSLC32:
+ case CSKY::LSRC32:
+ case CSKY::ASRC32:
+ MI.insert(std::next(MI.begin()), MCOperand::createReg(CSKY::C));
+ return MCDisassembler::Success;
+ case CSKY::MOVF32:
+ case CSKY::MOVT32:
+ case CSKY::MVC32:
+ case CSKY::MVCV32:
+ case CSKY::MVCV16:
+ case CSKY::INCT32:
+ case CSKY::INCF32:
+ case CSKY::DECT32:
+ case CSKY::DECF32:
+ case CSKY::DECGT32:
+ case CSKY::DECLT32:
+ case CSKY::DECNE32:
+ case CSKY::CLRF32:
+ case CSKY::CLRT32:
+ case CSKY::f2FSEL_S:
+ case CSKY::f2FSEL_D:
+ MI.insert(std::next(MI.begin()), MCOperand::createReg(CSKY::C));
+ return MCDisassembler::Success;
+ case CSKY::ADDC32:
+ case CSKY::ADDC16:
+ case CSKY::SUBC32:
+ case CSKY::SUBC16:
+ case CSKY::XSR32:
+ MI.insert(std::next(MI.begin()), MCOperand::createReg(CSKY::C));
+ MI.insert(MI.end(), MCOperand::createReg(CSKY::C));
+ return MCDisassembler::Success;
+ case CSKY::INS32:
+ MI.getOperand(3).setImm(MI.getOperand(3).getImm() +
+ MI.getOperand(4).getImm());
+ return MCDisassembler::Success;
+ }
+}
+
+static bool decodeFPUV3Instruction(MCInst &MI, uint32_t insn, uint64_t Address,
+ const void *DisAsm,
+ const MCSubtargetInfo &STI) {
+ LLVM_DEBUG(dbgs() << "Trying CSKY 32-bit fpuv3 table :\n");
+ if (!STI.getFeatureBits()[CSKY::FeatureFPUV3_HF] &&
+ !STI.getFeatureBits()[CSKY::FeatureFPUV3_SF] &&
+ !STI.getFeatureBits()[CSKY::FeatureFPUV3_DF])
+ return false;
+
+ DecodeStatus Result =
+ decodeInstruction(DecoderTableFPUV332, MI, insn, Address, DisAsm, STI);
+
+ if (Result == MCDisassembler::Fail) {
+ MI.clear();
+ return false;
+ }
+
+ return true;
+}
+
+DecodeStatus CSKYDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
+ ArrayRef<uint8_t> Bytes,
+ uint64_t Address,
+ raw_ostream &CS) const {
+
+ uint32_t Insn;
+ DecodeStatus Result = MCDisassembler::Fail;
+
+ Insn = support::endian::read16le(Bytes.data());
+
+ if ((Insn >> 14) == 0x3) {
+ if (Bytes.size() < 4) {
+ Size = 0;
+ return MCDisassembler::Fail;
+ }
+ Insn = (Insn << 16) | support::endian::read16le(&Bytes[2]);
+
+ if (decodeFPUV3Instruction(MI, Insn, Address, this, STI))
+ Result = MCDisassembler::Success;
+ else {
+ LLVM_DEBUG(dbgs() << "Trying CSKY 32-bit table :\n");
+ Result = decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI);
+ }
+
+ Size = 4;
+ } else {
+ if (Bytes.size() < 2) {
+ Size = 0;
+ return MCDisassembler::Fail;
+ }
+ LLVM_DEBUG(dbgs() << "Trying CSKY 16-bit table :\n");
+ Result = decodeInstruction(DecoderTable16, MI, Insn, Address, this, STI);
+ Size = 2;
+ }
+
+ handleCROperand(MI);
+
+ return Result;
+}
diff --git a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYInstPrinter.cpp b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYInstPrinter.cpp
index 07757f03c258b..3a0017d11e23b 100644
--- a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYInstPrinter.cpp
+++ b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYInstPrinter.cpp
@@ -9,16 +9,21 @@
// This class prints an CSKY MCInst to a .s file.
//
//===----------------------------------------------------------------------===//
-
#include "CSKYInstPrinter.h"
+#include "MCTargetDesc/CSKYBaseInfo.h"
+#include "MCTargetDesc/CSKYMCExpr.h"
+#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInst.h"
+#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
+#include "llvm/MC/MCSection.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/MCSymbol.h"
#include "llvm/Support/CommandLine.h"
+#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/FormattedStream.h"
@@ -55,6 +60,14 @@ bool CSKYInstPrinter::applyTargetSpecificCLOption(StringRef Opt) {
ArchRegNames = true;
return true;
}
+ if (Opt == "debug") {
+ DebugFlag = true;
+ return true;
+ }
+ if (Opt == "abi-names") {
+ ABIRegNames = true;
+ return true;
+ }
return false;
}
@@ -70,7 +83,11 @@ void CSKYInstPrinter::printInst(const MCInst *MI, uint64_t Address,
}
void CSKYInstPrinter::printRegName(raw_ostream &O, unsigned RegNo) const {
- O << getRegisterName(RegNo);
+ if (PrintBranchImmAsAddress)
+ O << getRegisterName(RegNo, ABIRegNames ? CSKY::ABIRegAltName
+ : CSKY::NoRegAltName);
+ else
+ O << getRegisterName(RegNo);
}
void CSKYInstPrinter::printFPRRegName(raw_ostream &O, unsigned RegNo) const {
@@ -87,15 +104,38 @@ void CSKYInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
const MCOperand &MO = MI->getOperand(OpNo);
if (MO.isReg()) {
- if (MO.getReg() == CSKY::C)
- O << "";
+ unsigned Reg = MO.getReg();
+ bool useABIName = false;
+ if (PrintBranchImmAsAddress)
+ useABIName = ABIRegNames;
else
- printRegName(O, MO.getReg());
+ useABIName = !ArchRegNames;
+
+ if (Reg == CSKY::C)
+ O << "";
+ else if (STI.getFeatureBits()[CSKY::FeatureJAVA]) {
+ if (Reg == CSKY::R23)
+ O << (useABIName ? "fp" : "r23");
+ else if (Reg == CSKY::R24)
+ O << (useABIName ? "top" : "r24");
+ else if (Reg == CSKY::R25)
+ O << (useABIName ? "bsp" : "r25");
+ else
+ printRegName(O, Reg);
+ } else
+ printRegName(O, Reg);
+
return;
}
if (MO.isImm()) {
- O << formatImm(MO.getImm());
+ uint64_t TSFlags = MII.get(MI->getOpcode()).TSFlags;
+
+ if (((TSFlags & CSKYII::AddrModeMask) != CSKYII::AddrModeNone) &&
+ PrintBranchImmAsAddress)
+ O << formatHex(MO.getImm());
+ else
+ O << MO.getImm();
return;
}
@@ -157,6 +197,22 @@ void CSKYInstPrinter::printCSKYSymbolOperand(const MCInst *MI, uint64_t Address,
}
}
+void CSKYInstPrinter::printPSRFlag(const MCInst *MI, unsigned OpNo,
+ const MCSubtargetInfo &STI, raw_ostream &O) {
+ auto V = MI->getOperand(OpNo).getImm();
+
+ ListSeparator LS;
+
+ if ((V >> 3) & 0x1)
+ O << LS << "ee";
+ if ((V >> 2) & 0x1)
+ O << LS << "ie";
+ if ((V >> 1) & 0x1)
+ O << LS << "fe";
+ if ((V >> 0) & 0x1)
+ O << LS << "af";
+}
+
void CSKYInstPrinter::printRegisterSeq(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI,
raw_ostream &O) {
diff --git a/llvm/test/MC/CSKY/basic-16bit.s b/llvm/test/MC/CSKY/basic-16bit.s
index 8323df13213d8..e341a1d1c31e0 100644
--- a/llvm/test/MC/CSKY/basic-16bit.s
+++ b/llvm/test/MC/CSKY/basic-16bit.s
@@ -1,191 +1,202 @@
# RUN: llvm-mc %s -triple=csky -show-encoding -csky-no-aliases -mattr=+e1 \
-# RUN: -mattr=+e2 -mattr=+btst16 | FileCheck -check-prefixes=CHECK-ASM %s
+# RUN: -mattr=+e2 -mattr=+btst16 | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=csky -mattr=+e1 -mattr=+e2 -mattr=+btst16 < %s \
+# RUN: | llvm-objdump --mattr=+e1 --mattr=+e2 --mattr=+btst16 -M no-aliases -M abi-names -d -r - \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM-AND-OBJ,CHECK-OBJ %s
-# CHECK-ASM: addi16 a0, a0, 2
+# CHECK-ASM-AND-OBJ: addi16 a0, a0, 2
# CHECK-ASM: encoding: [0x06,0x58]
addi16 a0, a0, 2
-# CHECK-ASM: addi16 a0, sp, 4
+# CHECK-ASM-AND-OBJ: addi16 a0, sp, 4
# CHECK-ASM: encoding: [0x01,0x18]
addi16 a0, sp, 4
-# CHECK-ASM: addi16 a0, a1, 2
+# CHECK-ASM-AND-OBJ: addi16 a0, a1, 2
# CHECK-ASM: encoding: [0x06,0x59]
addi16 a0, a1, 2
-# CHECK-ASM: addi16 sp, sp, 8
+# CHECK-ASM-AND-OBJ: addi16 sp, sp, 8
# CHECK-ASM: encoding: [0x02,0x14]
addi16 sp, sp, 8
-# CHECK-ASM: subi16 a0, a0, 2
+# CHECK-ASM-AND-OBJ: subi16 a0, a0, 2
# CHECK-ASM: encoding: [0x07,0x58]
subi16 a0, a0, 2
-# CHECK-ASM: subi16 a0, a1, 2
+# CHECK-ASM-AND-OBJ: subi16 a0, a1, 2
# CHECK-ASM: encoding: [0x07,0x59]
subi16 a0, a1, 2
-# CHECK-ASM: subi16 sp, sp, 8
+# CHECK-ASM-AND-OBJ: subi16 sp, sp, 8
# CHECK-ASM: encoding: [0x22,0x14]
subi16 sp, sp, 8
-# CHECK-ASM: lsli16 a0, a1, 2
+# CHECK-ASM-AND-OBJ: lsli16 a0, a1, 2
# CHECK-ASM: encoding: [0x02,0x41]
lsli16 a0, a1, 2
-# CHECK-ASM: lsri16 a0, a1, 2
+# CHECK-ASM-AND-OBJ: lsri16 a0, a1, 2
# CHECK-ASM: encoding: [0x02,0x49]
lsri16 a0, a1, 2
-# CHECK-ASM: asri16 a0, a1, 2
+# CHECK-ASM-AND-OBJ: asri16 a0, a1, 2
# CHECK-ASM: encoding: [0x02,0x51]
asri16 a0, a1, 2
-# CHECK-ASM: btsti16 a0, 2
+# CHECK-ASM-AND-OBJ: btsti16 a0, 2
# CHECK-ASM: encoding: [0xc2,0x38]
btsti16 a0, 2
-# CHECK-ASM: bclri16 a0, 2
+# CHECK-ASM-AND-OBJ: bclri16 a0, 2
# CHECK-ASM: encoding: [0x82,0x38]
bclri16 a0, 2
-# CHECK-ASM: bseti16 a0, 2
+# CHECK-ASM-AND-OBJ: bseti16 a0, 2
# CHECK-ASM: encoding: [0xa2,0x38]
bseti16 a0, 2
-# CHECK-ASM: cmpnei16 a0, 2
+# CHECK-ASM-AND-OBJ: cmpnei16 a0, 2
# CHECK-ASM: encoding: [0x42,0x38]
cmpnei16 a0, 2
-# CHECK-ASM: cmphsi16 a0, 2
+# CHECK-ASM-AND-OBJ: cmphsi16 a0, 2
# CHECK-ASM: encoding: [0x01,0x38]
cmphsi16 a0, 2
-# CHECK-ASM: cmplti16 a0, 2
+# CHECK-ASM-AND-OBJ: cmplti16 a0, 2
# CHECK-ASM: encoding: [0x21,0x38]
cmplti16 a0, 2
-# CHECK-ASM: movi16 a0, 2
+# CHECK-ASM-AND-OBJ: movi16 a0, 2
# CHECK-ASM: encoding: [0x02,0x30]
movi16 a0, 2
-# CHECK-ASM: addu16 a3, l0, l1
+# CHECK-ASM-AND-OBJ: addu16 a3, l0, l1
# CHECK-ASM: encoding: [0x74,0x5c]
addu16 a3, l0, l1
-# CHECK-ASM: subu16 a3, l0, l1
+# CHECK-ASM-AND-OBJ: subu16 a3, l0, l1
# CHECK-ASM: encoding: [0x75,0x5c]
subu16 a3, l0, l1
-# CHECK-ASM: and16 a3, l0
+# CHECK-ASM-AND-OBJ: and16 a3, l0
# CHECK-ASM: encoding: [0xd0,0x68]
and16 a3, l0
-# CHECK-ASM: andn16 a3, l0
+# CHECK-ASM-AND-OBJ: andn16 a3, l0
# CHECK-ASM: encoding: [0xd1,0x68]
andn16 a3, l0
-# CHECK-ASM: or16 a3, l0
+# CHECK-ASM-AND-OBJ: or16 a3, l0
# CHECK-ASM: encoding: [0xd0,0x6c]
or16 a3, l0
-# CHECK-ASM: xor16 a3, l0
+# CHECK-ASM-AND-OBJ: xor16 a3, l0
# CHECK-ASM: encoding: [0xd1,0x6c]
xor16 a3, l0
-# CHECK-ASM: nor16 a3, l0
+# CHECK-ASM-AND-OBJ: nor16 a3, l0
# CHECK-ASM: encoding: [0xd2,0x6c]
nor16 a3, l0
-# CHECK-ASM: lsl16 a3, l0
+# CHECK-ASM-AND-OBJ: lsl16 a3, l0
# CHECK-ASM: encoding: [0xd0,0x70]
lsl16 a3, l0
-# CHECK-ASM: rotl16 a3, l0
+# CHECK-ASM-AND-OBJ: rotl16 a3, l0
# CHECK-ASM: encoding: [0xd3,0x70]
rotl16 a3, l0
-# CHECK-ASM: lsr16 a3, l0
+# CHECK-ASM-AND-OBJ: lsr16 a3, l0
# CHECK-ASM: encoding: [0xd1,0x70]
lsr16 a3, l0
-# CHECK-ASM: asr16 a3, l0
+# CHECK-ASM-AND-OBJ: asr16 a3, l0
# CHECK-ASM: encoding: [0xd2,0x70]
asr16 a3, l0
-# CHECK-ASM: mult16 a3, l0
+# CHECK-ASM-AND-OBJ: mult16 a3, l0
# CHECK-ASM: encoding: [0xd0,0x7c]
mult16 a3, l0
-# CHECK-ASM: addc16 a3, l0
+# CHECK-ASM-AND-OBJ: addc16 a3, l0
# CHECK-ASM: encoding: [0xd1,0x60]
addc16 a3, l0
-# CHECK-ASM: subc16 a3, l0
+# CHECK-ASM-AND-OBJ: subc16 a3, l0
# CHECK-ASM: encoding: [0xd3,0x60]
subc16 a3, l0
+# CHECK-OBJ: ld16.b a0, (a0, 0x2)
# CHECK-ASM: ld16.b a0, (a0, 2)
# CHECK-ASM: encoding: [0x02,0x80]
ld16.b a0, (a0, 2)
+# CHECK-OBJ: ld16.h a0, (a0, 0x2)
# CHECK-ASM: ld16.h a0, (a0, 2)
# CHECK-ASM: encoding: [0x01,0x88]
ld16.h a0, (a0, 2)
+# CHECK-OBJ: ld16.w a0, (a0, 0x4)
# CHECK-ASM: ld16.w a0, (a0, 4)
# CHECK-ASM: encoding: [0x01,0x90]
ld16.w a0, (a0, 4)
+# CHECK-OBJ: ld16.w a0, (sp, 0x4)
# CHECK-ASM: ld16.w a0, (sp, 4)
# CHECK-ASM: encoding: [0x01,0x98]
ld16.w a0, (sp, 4)
+# CHECK-OBJ: st16.b a0, (a0, 0x2)
# CHECK-ASM: st16.b a0, (a0, 2)
# CHECK-ASM: encoding: [0x02,0xa0]
st16.b a0, (a0, 2)
+# CHECK-OBJ: st16.h a0, (a0, 0x2)
# CHECK-ASM: st16.h a0, (a0, 2)
# CHECK-ASM: encoding: [0x01,0xa8]
st16.h a0, (a0, 2)
+# CHECK-OBJ: st16.w a0, (a0, 0x4)
# CHECK-ASM: st16.w a0, (a0, 4)
# CHECK-ASM: encoding: [0x01,0xb0]
st16.w a0, (a0, 4)
+# CHECK-OBJ: st16.w a0, (sp, 0x4)
# CHECK-ASM: st16.w a0, (sp, 4)
# CHECK-ASM: encoding: [0x01,0xb8]
st16.w a0, (sp, 4)
-# CHECK-ASM: revb16 a3, l0
+# CHECK-ASM-AND-OBJ: revb16 a3, l0
# CHECK-ASM: encoding: [0xd2,0x78]
revb16 a3, l0
-# CHECK-ASM: revh16 a3, l0
+# CHECK-ASM-AND-OBJ: revh16 a3, l0
# CHECK-ASM: encoding: [0xd3,0x78]
revh16 a3, l0
-# CHECK-ASM: mvcv16 a3
+# CHECK-ASM-AND-OBJ: mvcv16 a3
# CHECK-ASM: encoding: [0xc3,0x64]
mvcv16 a3
-# CHECK-ASM: cmpne16 a3, l0
+# CHECK-ASM-AND-OBJ: cmpne16 a3, l0
# CHECK-ASM: encoding: [0x0e,0x65]
cmpne16 a3, l0
-# CHECK-ASM: cmphs16 a3, l0
+# CHECK-ASM-AND-OBJ: cmphs16 a3, l0
# CHECK-ASM: encoding: [0x0c,0x65]
cmphs16 a3, l0
-# CHECK-ASM: cmplt16 a3, l0
+# CHECK-ASM-AND-OBJ: cmplt16 a3, l0
# CHECK-ASM: encoding: [0x0d,0x65]
cmplt16 a3, l0
-# CHECK-ASM: tst16 a3, l0
+# CHECK-ASM-AND-OBJ: tst16 a3, l0
# CHECK-ASM: encoding: [0x0e,0x69]
tst16 a3, l0
-# CHECK-ASM: tstnbz16 a3
+# CHECK-ASM-AND-OBJ: tstnbz16 a3
# CHECK-ASM: encoding: [0x0f,0x68]
tstnbz16 a3
@@ -207,11 +218,11 @@ bt16 .L.test2
.L.test3:
bf16 .L.test3
-# CHECK-ASM: jmp16 a3
+# CHECK-ASM-AND-OBJ: jmp16 a3
# CHECK-ASM: encoding: [0x0c,0x78]
jmp16 a3
-# CHECK-ASM: jsr16 a3
+# CHECK-ASM-AND-OBJ: jsr16 a3
# CHECK-ASM: encoding: [0xcd,0x7b]
jsr16 a3
diff --git a/llvm/test/MC/CSKY/basic.s b/llvm/test/MC/CSKY/basic.s
index 69f41bb090308..3a8d3868f2957 100644
--- a/llvm/test/MC/CSKY/basic.s
+++ b/llvm/test/MC/CSKY/basic.s
@@ -1,463 +1,476 @@
# RUN: llvm-mc %s -triple=csky -show-encoding -csky-no-aliases -mattr=+e2 -mattr=+2e3 \
-# RUN: -mattr=+mp1e2 | FileCheck -check-prefixes=CHECK-ASM %s
+# RUN: -mattr=+mp1e2 | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=csky -mattr=+e2 -mattr=+2e3 -mattr=+mp1e2 < %s \
+# RUN: | llvm-objdump --mattr=+e2 --mattr=+2e3 --mattr=+mp1e2 -M no-aliases -M abi-names -d -r - \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM-AND-OBJ,CHECK-OBJ %s
-# CHECK-ASM: addi32 a0, sp, 2
+# CHECK-ASM-AND-OBJ: addi32 a0, sp, 2
# CHECK-ASM: encoding: [0x0e,0xe4,0x01,0x00]
addi32 a0, sp, 2
-# CHECK-ASM: subi32 a0, sp, 2
+# CHECK-ASM-AND-OBJ: subi32 a0, sp, 2
# CHECK-ASM: encoding: [0x0e,0xe4,0x01,0x10]
subi32 a0, sp, 2
-# CHECK-ASM: andi32 a0, sp, 2
+# CHECK-ASM-AND-OBJ: andi32 a0, sp, 2
# CHECK-ASM: encoding: [0x0e,0xe4,0x02,0x20]
andi32 a0, sp, 2
-# CHECK-ASM: andni32 a0, sp, 2
+# CHECK-ASM-AND-OBJ: andni32 a0, sp, 2
# CHECK-ASM: encoding: [0x0e,0xe4,0x02,0x30]
andni32 a0, sp, 2
-# CHECK-ASM: xori32 a0, sp, 2
+# CHECK-ASM-AND-OBJ: xori32 a0, sp, 2
# CHECK-ASM: encoding: [0x0e,0xe4,0x02,0x40]
xori32 a0, sp, 2
-# CHECK-ASM: lsli32 a0, sp, 2
+# CHECK-ASM-AND-OBJ: lsli32 a0, sp, 2
# CHECK-ASM: encoding: [0x4e,0xc4,0x20,0x48]
lsli32 a0, sp, 2
-# CHECK-ASM: lsri32 a0, sp, 2
+# CHECK-ASM-AND-OBJ: lsri32 a0, sp, 2
# CHECK-ASM: encoding: [0x4e,0xc4,0x40,0x48]
lsri32 a0, sp, 2
-# CHECK-ASM: asri32 a0, sp, 2
+# CHECK-ASM-AND-OBJ: asri32 a0, sp, 2
# CHECK-ASM: encoding: [0x4e,0xc4,0x80,0x48]
asri32 a0, sp, 2
-# CHECK-ASM: ori32 a0, sp, 2
+# CHECK-ASM-AND-OBJ: ori32 a0, sp, 2
# CHECK-ASM: encoding: [0x0e,0xec,0x02,0x00]
ori32 a0, sp, 2
-# CHECK-ASM: rotli32 a0, sp, 2
+# CHECK-ASM-AND-OBJ: rotli32 a0, sp, 2
# CHECK-ASM: encoding: [0x4e,0xc4,0x00,0x49]
rotli32 a0, sp, 2
-# CHECK-ASM: incf32 a0, sp, 2
+# CHECK-ASM-AND-OBJ: incf32 a0, sp, 2
# CHECK-ASM: encoding: [0x0e,0xc4,0x22,0x0c]
incf32 a0, sp, 2
-# CHECK-ASM: inct32 a0, sp, 2
+# CHECK-ASM-AND-OBJ: inct32 a0, sp, 2
# CHECK-ASM: encoding: [0x0e,0xc4,0x42,0x0c]
inct32 a0, sp, 2
-# CHECK-ASM: decf32 a0, sp, 2
+# CHECK-ASM-AND-OBJ: decf32 a0, sp, 2
# CHECK-ASM: encoding: [0x0e,0xc4,0x82,0x0c]
decf32 a0, sp, 2
-# CHECK-ASM: dect32 a0, sp, 2
+# CHECK-ASM-AND-OBJ: dect32 a0, sp, 2
# CHECK-ASM: encoding: [0x0e,0xc4,0x02,0x0d]
dect32 a0, sp, 2
-# CHECK-ASM: decgt32 a0, sp, 2
+# CHECK-ASM-AND-OBJ: decgt32 a0, sp, 2
# CHECK-ASM: encoding: [0x4e,0xc4,0x20,0x10]
decgt32 a0, sp, 2
-# CHECK-ASM: declt32 a0, sp, 2
+# CHECK-ASM-AND-OBJ: declt32 a0, sp, 2
# CHECK-ASM: encoding: [0x4e,0xc4,0x40,0x10]
declt32 a0, sp, 2
-# CHECK-ASM: decne32 a0, sp, 2
+# CHECK-ASM-AND-OBJ: decne32 a0, sp, 2
# CHECK-ASM: encoding: [0x4e,0xc4,0x80,0x10]
decne32 a0, sp, 2
-# CHECK-ASM: btsti32 a0, 2
+# CHECK-ASM-AND-OBJ: btsti32 a0, 2
# CHECK-ASM: encoding: [0x40,0xc4,0x80,0x28]
btsti32 a0, 2
-# CHECK-ASM: bclri32 a0, sp, 2
+# CHECK-ASM-AND-OBJ: bclri32 a0, sp, 2
# CHECK-ASM: encoding: [0x4e,0xc4,0x20,0x28]
bclri32 a0, sp, 2
-# CHECK-ASM: bseti32 a0, sp, 2
+# CHECK-ASM-AND-OBJ: bseti32 a0, sp, 2
# CHECK-ASM: encoding: [0x4e,0xc4,0x40,0x28]
bseti32 a0, sp, 2
-# CHECK-ASM: cmpnei32 a0, 2
+# CHECK-ASM-AND-OBJ: cmpnei32 a0, 2
# CHECK-ASM: encoding: [0x40,0xeb,0x02,0x00]
cmpnei32 a0, 2
-# CHECK-ASM: cmphsi32 a0, 2
+# CHECK-ASM-AND-OBJ: cmphsi32 a0, 2
# CHECK-ASM: encoding: [0x00,0xeb,0x01,0x00]
cmphsi32 a0, 2
-# CHECK-ASM: cmplti32 a0, 2
+# CHECK-ASM-AND-OBJ: cmplti32 a0, 2
# CHECK-ASM: encoding: [0x20,0xeb,0x01,0x00]
cmplti32 a0, 2
-# CHECK-ASM: movi32 a0, 2
+# CHECK-ASM-AND-OBJ: movi32 a0, 2
# CHECK-ASM: encoding: [0x00,0xea,0x02,0x00]
movi32 a0, 2
-# CHECK-ASM: movih32 a0, 2
+# CHECK-ASM-AND-OBJ: movih32 a0, 2
# CHECK-ASM: encoding: [0x20,0xea,0x02,0x00]
movih32 a0, 2
-# CHECK-ASM: addu32 a3, l0, l1
+# CHECK-ASM-AND-OBJ: addu32 a3, l0, l1
# CHECK-ASM: encoding: [0xa4,0xc4,0x23,0x00]
addu32 a3, l0, l1
-# CHECK-ASM: subu32 a3, l0, l1
+# CHECK-ASM-AND-OBJ: subu32 a3, l0, l1
# CHECK-ASM: encoding: [0xa4,0xc4,0x83,0x00]
subu32 a3, l0, l1
-# CHECK-ASM: and32 a3, l0, l1
+# CHECK-ASM-AND-OBJ: and32 a3, l0, l1
# CHECK-ASM: encoding: [0xa4,0xc4,0x23,0x20]
and32 a3, l0, l1
-# CHECK-ASM: andn32 a3, l0, l1
+# CHECK-ASM-AND-OBJ: andn32 a3, l0, l1
# CHECK-ASM: encoding: [0xa4,0xc4,0x43,0x20]
andn32 a3, l0, l1
-# CHECK-ASM: or32 a3, l0, l1
+# CHECK-ASM-AND-OBJ: or32 a3, l0, l1
# CHECK-ASM: encoding: [0xa4,0xc4,0x23,0x24]
or32 a3, l0, l1
-# CHECK-ASM: xor32 a3, l0, l1
+# CHECK-ASM-AND-OBJ: xor32 a3, l0, l1
# CHECK-ASM: encoding: [0xa4,0xc4,0x43,0x24]
xor32 a3, l0, l1
-# CHECK-ASM: nor32 a3, l0, l1
+# CHECK-ASM-AND-OBJ: nor32 a3, l0, l1
# CHECK-ASM: encoding: [0xa4,0xc4,0x83,0x24]
nor32 a3, l0, l1
-# CHECK-ASM: lsl32 a3, l0, l1
+# CHECK-ASM-AND-OBJ: lsl32 a3, l0, l1
# CHECK-ASM: encoding: [0xa4,0xc4,0x23,0x40]
lsl32 a3, l0, l1
-# CHECK-ASM: rotl32 a3, l0, l1
+# CHECK-ASM-AND-OBJ: rotl32 a3, l0, l1
# CHECK-ASM: encoding: [0xa4,0xc4,0x03,0x41]
rotl32 a3, l0, l1
-# CHECK-ASM: lsr32 a3, l0, l1
+# CHECK-ASM-AND-OBJ: lsr32 a3, l0, l1
# CHECK-ASM: encoding: [0xa4,0xc4,0x43,0x40]
lsr32 a3, l0, l1
-# CHECK-ASM: asr32 a3, l0, l1
+# CHECK-ASM-AND-OBJ: asr32 a3, l0, l1
# CHECK-ASM: encoding: [0xa4,0xc4,0x83,0x40]
asr32 a3, l0, l1
-# CHECK-ASM: lslc32 a0, sp, 2
+# CHECK-ASM-AND-OBJ: lslc32 a0, sp, 2
# CHECK-ASM: encoding: [0x2e,0xc4,0x20,0x4c]
lslc32 a0, sp, 2
-# CHECK-ASM: lsrc32 a0, sp, 2
+# CHECK-ASM-AND-OBJ: lsrc32 a0, sp, 2
# CHECK-ASM: encoding: [0x2e,0xc4,0x40,0x4c]
lsrc32 a0, sp, 2
-# CHECK-ASM: asrc32 a0, sp, 2
+# CHECK-ASM-AND-OBJ: asrc32 a0, sp, 2
# CHECK-ASM: encoding: [0x2e,0xc4,0x80,0x4c]
asrc32 a0, sp, 2
-# CHECK-ASM: xsr32 a0, sp, 2
+# CHECK-ASM-AND-OBJ: xsr32 a0, sp, 2
# CHECK-ASM: encoding: [0x2e,0xc4,0x00,0x4d]
xsr32 a0, sp, 2
-# CHECK-ASM: bmaski32 a3, 17
+# CHECK-ASM-AND-OBJ: bmaski32 a3, 17
# CHECK-ASM: encoding: [0x00,0xc6,0x23,0x50]
bmaski32 a3, 17
-# CHECK-ASM: mult32 a3, l0, l1
+# CHECK-ASM-AND-OBJ: mult32 a3, l0, l1
# CHECK-ASM: encoding: [0xa4,0xc4,0x23,0x84]
mult32 a3, l0, l1
-# CHECK-ASM: divs32 a3, l0, l1
+# CHECK-ASM-AND-OBJ: divs32 a3, l0, l1
# CHECK-ASM: encoding: [0xa4,0xc4,0x43,0x80]
divs32 a3, l0, l1
-# CHECK-ASM: divu32 a3, l0, l1
+# CHECK-ASM-AND-OBJ: divu32 a3, l0, l1
# CHECK-ASM: encoding: [0xa4,0xc4,0x23,0x80]
divu32 a3, l0, l1
-# CHECK-ASM: ixh32 a3, l0, l1
+# CHECK-ASM-AND-OBJ: ixh32 a3, l0, l1
# CHECK-ASM: encoding: [0xa4,0xc4,0x23,0x08]
ixh32 a3, l0, l1
-# CHECK-ASM: ixw32 a3, l0, l1
+# CHECK-ASM-AND-OBJ: ixw32 a3, l0, l1
# CHECK-ASM: encoding: [0xa4,0xc4,0x43,0x08]
ixw32 a3, l0, l1
-# CHECK-ASM: ixd32 a3, l0, l1
+# CHECK-ASM-AND-OBJ: ixd32 a3, l0, l1
# CHECK-ASM: encoding: [0xa4,0xc4,0x83,0x08]
ixd32 a3, l0, l1
-# CHECK-ASM: addc32 a3, l0, l1
+# CHECK-ASM-AND-OBJ: addc32 a3, l0, l1
# CHECK-ASM: encoding: [0xa4,0xc4,0x43,0x00]
addc32 a3, l0, l1
-# CHECK-ASM: subc32 a3, l0, l1
+# CHECK-ASM-AND-OBJ: subc32 a3, l0, l1
# CHECK-ASM: encoding: [0xa4,0xc4,0x03,0x01]
subc32 a3, l0, l1
+# CHECK-OBJ: ld32.b a0, (sp, 0x2)
# CHECK-ASM: ld32.b a0, (sp, 2)
# CHECK-ASM: encoding: [0x0e,0xd8,0x02,0x00]
ld32.b a0, (sp, 2)
+# CHECK-OBJ: ld32.bs a0, (sp, 0x2)
# CHECK-ASM: ld32.bs a0, (sp, 2)
# CHECK-ASM: encoding: [0x0e,0xd8,0x02,0x40]
ld32.bs a0, (sp, 2)
+# CHECK-OBJ: ld32.h a0, (sp, 0x2)
# CHECK-ASM: ld32.h a0, (sp, 2)
# CHECK-ASM: encoding: [0x0e,0xd8,0x01,0x10]
ld32.h a0, (sp, 2)
+# CHECK-OBJ: ld32.hs a0, (sp, 0x2)
# CHECK-ASM: ld32.hs a0, (sp, 2)
# CHECK-ASM: encoding: [0x0e,0xd8,0x01,0x50]
ld32.hs a0, (sp, 2)
+# CHECK-OBJ: ld32.w a0, (sp, 0x4)
# CHECK-ASM: ld32.w a0, (sp, 4)
# CHECK-ASM: encoding: [0x0e,0xd8,0x01,0x20]
ld32.w a0, (sp, 4)
-# CHECK-ASM: ldr32.b a0, (sp, l1 << 2)
+# CHECK-ASM-AND-OBJ: ldr32.b a0, (sp, l1 << 2)
# CHECK-ASM: encoding: [0xae,0xd0,0x80,0x00]
ldr32.b a0, (sp, l1 << 2)
+# CHECK-OBJ: ldex32.w a0, (sp, 0x4)
# CHECK-ASM: ldex32.w a0, (sp, 4)
# CHECK-ASM: encoding: [0x0e,0xd8,0x01,0x70]
ldex32.w a0, (sp, 4)
-# CHECK-ASM: ldr32.bs a0, (sp, l1 << 2)
+# CHECK-ASM-AND-OBJ: ldr32.bs a0, (sp, l1 << 2)
# CHECK-ASM: encoding: [0xae,0xd0,0x80,0x10]
ldr32.bs a0, (sp, l1 << 2)
-# CHECK-ASM: ldr32.h a0, (sp, l1 << 3)
+# CHECK-ASM-AND-OBJ: ldr32.h a0, (sp, l1 << 3)
# CHECK-ASM: encoding: [0xae,0xd0,0x00,0x05]
ldr32.h a0, (sp, l1 << 3)
-# CHECK-ASM: ldr32.hs a0, (sp, l1 << 3)
+# CHECK-ASM-AND-OBJ: ldr32.hs a0, (sp, l1 << 3)
# CHECK-ASM: encoding: [0xae,0xd0,0x00,0x15]
ldr32.hs a0, (sp, l1 << 3)
-# CHECK-ASM: ldr32.w a0, (sp, l1 << 3)
+# CHECK-ASM-AND-OBJ: ldr32.w a0, (sp, l1 << 3)
# CHECK-ASM: encoding: [0xae,0xd0,0x00,0x09]
ldr32.w a0, (sp, l1 << 3)
+# CHECK-OBJ: st32.b a0, (sp, 0x2)
# CHECK-ASM: st32.b a0, (sp, 2)
# CHECK-ASM: encoding: [0x0e,0xdc,0x02,0x00]
st32.b a0, (sp, 2)
+# CHECK-OBJ: st32.h a0, (sp, 0x2)
# CHECK-ASM: st32.h a0, (sp, 2)
# CHECK-ASM: encoding: [0x0e,0xdc,0x01,0x10]
st32.h a0, (sp, 2)
+# CHECK-OBJ: st32.w a0, (sp, 0x4)
# CHECK-ASM: st32.w a0, (sp, 4)
# CHECK-ASM: encoding: [0x0e,0xdc,0x01,0x20]
st32.w a0, (sp, 4)
+# CHECK-OBJ: stex32.w a0, (sp, 0x4)
# CHECK-ASM: stex32.w a0, (sp, 4)
# CHECK-ASM: encoding: [0x0e,0xdc,0x01,0x70]
stex32.w a0, (sp, 4)
-# CHECK-ASM: str32.b a0, (sp, l1 << 2)
+# CHECK-ASM-AND-OBJ: str32.b a0, (sp, l1 << 2)
# CHECK-ASM: encoding: [0xae,0xd4,0x80,0x00]
str32.b a0, (sp, l1 << 2)
-# CHECK-ASM: str32.h a0, (sp, l1 << 3)
+# CHECK-ASM-AND-OBJ: str32.h a0, (sp, l1 << 3)
# CHECK-ASM: encoding: [0xae,0xd4,0x00,0x05]
str32.h a0, (sp, l1 << 3)
-# CHECK-ASM: str32.w a0, (sp, l1 << 3)
+# CHECK-ASM-AND-OBJ: str32.w a0, (sp, l1 << 3)
# CHECK-ASM: encoding: [0xae,0xd4,0x00,0x09]
str32.w a0, (sp, l1 << 3)
-# CHECK-ASM: ldm32 a1-a2, (a0)
+# CHECK-ASM-AND-OBJ: ldm32 a1-a2, (a0)
# CHECK-ASM: encoding: [0x20,0xd0,0x21,0x1c]
ldm32 a1-a2, (a0)
-# CHECK-ASM: stm32 a1-a2, (a0)
+# CHECK-ASM-AND-OBJ: stm32 a1-a2, (a0)
# CHECK-ASM: encoding: [0x20,0xd4,0x21,0x1c]
stm32 a1-a2, (a0)
-# CHECK-ASM: ldm32 l0-l3, (a0)
+# CHECK-ASM-AND-OBJ: ldm32 l0-l3, (a0)
# CHECK-ASM: encoding: [0x80,0xd0,0x23,0x1c]
ldq32 r4-r7, (a0)
-# CHECK-ASM: stm32 l0-l3, (a0)
+# CHECK-ASM-AND-OBJ: stm32 l0-l3, (a0)
# CHECK-ASM: encoding: [0x80,0xd4,0x23,0x1c]
stq32 r4-r7, (a0)
-# CHECK-ASM: brev32 a3, l0
+# CHECK-ASM-AND-OBJ: brev32 a3, l0
# CHECK-ASM: encoding: [0x04,0xc4,0x03,0x62]
brev32 a3, l0
-# CHECK-ASM: abs32 a3, l0
+# CHECK-ASM-AND-OBJ: abs32 a3, l0
# CHECK-ASM: encoding: [0x04,0xc4,0x03,0x02]
abs32 a3, l0
-# CHECK-ASM: bgenr32 a3, l0
+# CHECK-ASM-AND-OBJ: bgenr32 a3, l0
# CHECK-ASM: encoding: [0x04,0xc4,0x43,0x50]
bgenr32 a3, l0
-# CHECK-ASM: revb32 a3, l0
+# CHECK-ASM-AND-OBJ: revb32 a3, l0
# CHECK-ASM: encoding: [0x04,0xc4,0x83,0x60]
revb32 a3, l0
-# CHECK-ASM: revh32 a3, l0
+# CHECK-ASM-AND-OBJ: revh32 a3, l0
# CHECK-ASM: encoding: [0x04,0xc4,0x03,0x61]
revh32 a3, l0
-# CHECK-ASM: ff0.32 a3, l0
+# CHECK-ASM-AND-OBJ: ff0.32 a3, l0
# CHECK-ASM: encoding: [0x04,0xc4,0x23,0x7c]
ff0.32 a3, l0
-# CHECK-ASM: ff1.32 a3, l0
+# CHECK-ASM-AND-OBJ: ff1.32 a3, l0
# CHECK-ASM: encoding: [0x04,0xc4,0x43,0x7c]
ff1.32 a3, l0
-# CHECK-ASM: xtrb0.32 a3, l0
+# CHECK-ASM-AND-OBJ: xtrb0.32 a3, l0
# CHECK-ASM: encoding: [0x04,0xc4,0x23,0x70]
xtrb0.32 a3, l0
-# CHECK-ASM: xtrb1.32 a3, l0
+# CHECK-ASM-AND-OBJ: xtrb1.32 a3, l0
# CHECK-ASM: encoding: [0x04,0xc4,0x43,0x70]
xtrb1.32 a3, l0
-# CHECK-ASM: xtrb2.32 a3, l0
+# CHECK-ASM-AND-OBJ: xtrb2.32 a3, l0
# CHECK-ASM: encoding: [0x04,0xc4,0x83,0x70]
xtrb2.32 a3, l0
-# CHECK-ASM: xtrb3.32 a3, l0
+# CHECK-ASM-AND-OBJ: xtrb3.32 a3, l0
# CHECK-ASM: encoding: [0x04,0xc4,0x03,0x71]
xtrb3.32 a3, l0
-# CHECK-ASM: mvc32 a3
+# CHECK-ASM-AND-OBJ: mvc32 a3
# CHECK-ASM: encoding: [0x00,0xc4,0x03,0x05]
mvc32 a3
-# CHECK-ASM: mvcv32 a3
+# CHECK-ASM-AND-OBJ: mvcv32 a3
# CHECK-ASM: encoding: [0x00,0xc4,0x03,0x06]
mvcv32 a3
-# CHECK-ASM: cmpne32 a3, l0
+# CHECK-ASM-AND-OBJ: cmpne32 a3, l0
# CHECK-ASM: encoding: [0x83,0xc4,0x80,0x04]
cmpne32 a3, l0
-# CHECK-ASM: cmphs32 a3, l0
+# CHECK-ASM-AND-OBJ: cmphs32 a3, l0
# CHECK-ASM: encoding: [0x83,0xc4,0x20,0x04]
cmphs32 a3, l0
-# CHECK-ASM: cmplt32 a3, l0
+# CHECK-ASM-AND-OBJ: cmplt32 a3, l0
# CHECK-ASM: encoding: [0x83,0xc4,0x40,0x04]
cmplt32 a3, l0
-# CHECK-ASM: zext32 a3, l0, 7, 0
+# CHECK-ASM-AND-OBJ: zext32 a3, l0, 7, 0
# CHECK-ASM: encoding: [0x04,0xc4,0xe3,0x54]
zext32 a3, l0, 7, 0
-# CHECK-ASM: sext32 a3, l0, 7, 0
+# CHECK-ASM-AND-OBJ: sext32 a3, l0, 7, 0
# CHECK-ASM: encoding: [0x04,0xc4,0xe3,0x58]
sext32 a3, l0, 7, 0
-# CHECK-ASM: ldm32 l1-l3, (a0)
+# CHECK-ASM-AND-OBJ: ldm32 l1-l3, (a0)
# CHECK-ASM: encoding: [0xa0,0xd0,0x22,0x1c]
ldm32 r5-r7, (a0)
-# CHECK-ASM: stm32 l1-l3, (a0)
+# CHECK-ASM-AND-OBJ: stm32 l1-l3, (a0)
# CHECK-ASM: encoding: [0xa0,0xd4,0x22,0x1c]
stm32 r5-r7, (a0)
-# CHECK-ASM: setc32
+# CHECK-ASM-AND-OBJ: setc32
# CHECK-ASM: encoding: [0x00,0xc4,0x20,0x04]
setc32
-# CHECK-ASM: clrc32
+# CHECK-ASM-AND-OBJ: clrc32
# CHECK-ASM: encoding: [0x00,0xc4,0x80,0x04]
clrc32
-# CHECK-ASM: tst32 a3, l0
+# CHECK-ASM-AND-OBJ: tst32 a3, l0
# CHECK-ASM: encoding: [0x83,0xc4,0x80,0x20]
tst32 a3, l0
-# CHECK-ASM: tstnbz32 a3
+# CHECK-ASM-AND-OBJ: tstnbz32 a3
# CHECK-ASM: encoding: [0x03,0xc4,0x00,0x21]
tstnbz32 a3
-# CHECK-ASM: clrf32 a3
+# CHECK-ASM-AND-OBJ: clrf32 a3
# CHECK-ASM: encoding: [0x60,0xc4,0x20,0x2c]
clrf32 a3
-# CHECK-ASM: clrt32 a3
+# CHECK-ASM-AND-OBJ: clrt32 a3
# CHECK-ASM: encoding: [0x60,0xc4,0x40,0x2c]
clrt32 a3
-# CHECK-ASM: bar.brwarw
+# CHECK-ASM-AND-OBJ: bar.brwarw
# CHECK-ASM: encoding: [0x00,0xc0,0x2f,0x84]
bar.brwarw
-# CHECK-ASM: bar.brwarws
+# CHECK-ASM-AND-OBJ: bar.brwarws
# CHECK-ASM: encoding: [0x00,0xc2,0x2f,0x84]
bar.brwarws
-# CHECK-ASM: bar.brarw
+# CHECK-ASM-AND-OBJ: bar.brarw
# CHECK-ASM: encoding: [0x00,0xc0,0x27,0x84]
bar.brarw
-# CHECK-ASM: bar.brarws
+# CHECK-ASM-AND-OBJ: bar.brarws
# CHECK-ASM: encoding: [0x00,0xc2,0x27,0x84]
bar.brarws
-# CHECK-ASM: bar.brwaw
+# CHECK-ASM-AND-OBJ: bar.brwaw
# CHECK-ASM: encoding: [0x00,0xc0,0x2e,0x84]
bar.brwaw
-# CHECK-ASM: bar.brwaws
+# CHECK-ASM-AND-OBJ: bar.brwaws
# CHECK-ASM: encoding: [0x00,0xc2,0x2e,0x84]
bar.brwaws
-# CHECK-ASM: bar.brar
+# CHECK-ASM-AND-OBJ: bar.brar
# CHECK-ASM: encoding: [0x00,0xc0,0x25,0x84]
bar.brar
-# CHECK-ASM: bar.brars
+# CHECK-ASM-AND-OBJ: bar.brars
# CHECK-ASM: encoding: [0x00,0xc2,0x25,0x84]
bar.brars
-# CHECK-ASM: bar.bwaw
+# CHECK-ASM-AND-OBJ: bar.bwaw
# CHECK-ASM: encoding: [0x00,0xc0,0x2a,0x84]
bar.bwaw
-# CHECK-ASM: bar.bwaws
+# CHECK-ASM-AND-OBJ: bar.bwaws
# CHECK-ASM: encoding: [0x00,0xc2,0x2a,0x84]
bar.bwaws
-# CHECK-ASM: sync32
+# CHECK-ASM-AND-OBJ: sync32
# CHECK-ASM: encoding: [0x00,0xc0,0x20,0x04]
sync32
-# CHECK-ASM: sync32.s
+# CHECK-ASM-AND-OBJ: sync32.s
# CHECK-ASM: encoding: [0x00,0xc2,0x20,0x04]
sync32.s
-# CHECK-ASM: sync32.i
+# CHECK-ASM-AND-OBJ: sync32.i
# CHECK-ASM: encoding: [0x20,0xc0,0x20,0x04]
sync32.i
-# CHECK-ASM: sync32.is
+# CHECK-ASM-AND-OBJ: sync32.is
# CHECK-ASM: encoding: [0x20,0xc2,0x20,0x04]
sync32.is
-# CHECK-ASM: rfi32
+# CHECK-ASM-AND-OBJ: rfi32
# CHECK-ASM: encoding: [0x00,0xc0,0x20,0x44]
rfi32
-# CHECK-ASM: stop32
+# CHECK-ASM-AND-OBJ: stop32
# CHECK-ASM: encoding: [0x00,0xc0,0x20,0x48]
stop32
-# CHECK-ASM: wait32
+# CHECK-ASM-AND-OBJ: wait32
# CHECK-ASM: encoding: [0x00,0xc0,0x20,0x4c]
wait32
-# CHECK-ASM: doze32
+# CHECK-ASM-AND-OBJ: doze32
# CHECK-ASM: encoding: [0x00,0xc0,0x20,0x50]
doze32
diff --git a/llvm/test/MC/CSKY/fpuv2.s b/llvm/test/MC/CSKY/fpuv2.s
index 7d4e7a4682bec..714d18342a271 100644
--- a/llvm/test/MC/CSKY/fpuv2.s
+++ b/llvm/test/MC/CSKY/fpuv2.s
@@ -1,5 +1,8 @@
# RUN: llvm-mc %s -triple=csky -show-encoding -csky-no-aliases -mattr=+fpuv2_sf -mattr=+fpuv2_df \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=csky -mattr=+fpuv2_sf -mattr=+fpuv2_df < %s \
+# RUN: | llvm-objdump --mattr=+fpuv2_sf --mattr=+fpuv2_df -M no-aliases -M abi-names -d -r - \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM-AND-OBJ %s
# CHECK-ASM-AND-OBJ: fldms vr1-vr2, (a1)
# CHECK-ASM: encoding: [0x21,0xf4,0x01,0x30]
diff --git a/llvm/test/MC/CSKY/fpuv3.s b/llvm/test/MC/CSKY/fpuv3.s
index 071ad10cfbe43..a084aa6d2c73e 100644
--- a/llvm/test/MC/CSKY/fpuv3.s
+++ b/llvm/test/MC/CSKY/fpuv3.s
@@ -1,5 +1,8 @@
# RUN: llvm-mc %s -triple=csky -show-encoding -csky-no-aliases -mattr=+fpuv3_sf,+fpuv3_df \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=csky -mattr=+fpuv3_sf,+fpuv3_df < %s \
+# RUN: | llvm-objdump --mattr=+fpuv3_sf,+fpuv3_df -M no-aliases -M abi-names -d -r - \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM-AND-OBJ %s
# CHECK-ASM-AND-OBJ: fldm.32 vr1-vr2, (a1)
# CHECK-ASM: encoding: [0x21,0xf4,0x01,0x30]
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