[PATCH] D119217: [X86] Update register RCL/RCR by 1 and immediate scheduling for Intel CPUs

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: RKSimon, spatel, lebedev.ri, pengfei.
Herald added subscribers: gbedwell, hiraditya.
Herald added a reviewer: andreadb.
craig.topper requested review of this revision.
Herald added a project: LLVM.

Most Intel CPU scheduler files lumped the immediate and 1 instructions
together, but uops.info shows they are quite different.

For the most part the by 1 instructions were pretty accurate to the uops.info
data except the latency was 3 instead of 2 as uops.info indicates.

The by immediate instructions need 7 or 8 uops and have higher latency.

It looks like the 8-bit by immediate instructions may need even more
uops, but I just lumped them with the 16/32/64.

Noticed while checking out PR53648. So mostly I cared about the by 1
instructions.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D119217

Files:
  llvm/lib/Target/X86/X86SchedBroadwell.td
  llvm/lib/Target/X86/X86SchedHaswell.td
  llvm/lib/Target/X86/X86SchedIceLake.td
  llvm/lib/Target/X86/X86SchedSandyBridge.td
  llvm/lib/Target/X86/X86SchedSkylakeClient.td
  llvm/lib/Target/X86/X86SchedSkylakeServer.td
  llvm/test/tools/llvm-mca/X86/Barcelona/resources-x86_64.s
  llvm/test/tools/llvm-mca/X86/Broadwell/resources-x86_64.s
  llvm/test/tools/llvm-mca/X86/Generic/resources-x86_64.s
  llvm/test/tools/llvm-mca/X86/Haswell/resources-x86_64.s
  llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-x86_64.s
  llvm/test/tools/llvm-mca/X86/SandyBridge/resources-x86_64.s
  llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-x86_64.s
  llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-x86_64.s

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