[PATCH] D119115: [RISCV] Improve insert_vector_elt for fixed mask registers.

[Jianjian Guan via Phabricator via llvm-commits]

jacquesguan added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-i1.ll:109
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT:    vmv.s.x v8, a0
-; CHECK-NEXT:    vmv.v.i v9, 0
-; CHECK-NEXT:    vmerge.vim v9, v9, 1, v0
-; CHECK-NEXT:    vsetivli zero, 2, e8, mf2, tu, mu
-; CHECK-NEXT:    vslideup.vi v9, v8, 1
-; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT:    vand.vi v8, v9, 1
-; CHECK-NEXT:    vmsne.vi v0, v8, 0
+; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    slli a0, a0, 1
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craig.topper wrote:
> The upper xlen-1 bits of a0 have an unknown value. The value of %elt is only in the lower bit. You need to mask off the other bits. A mask would only not be needed if the i1 was passed with zeroext attribute.
Done, thanks.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D119115/new/

https://reviews.llvm.org/D119115