[PATCH] D118298: [Spill2Reg][1/9] Initial commit. This is boilerplate code.

[Vasileios Porpodas via Phabricator via llvm-commits]

vporpo added a comment.

Yes, a two-tier spilling scheme might make sense for some targets: first spill to consecutive lanes in the vector, and then spill the vectors to memory.  I think though that in x86 it may be a lot trickier to check when this will perform better than standard spills to stack.


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https://reviews.llvm.org/D118298