[PATCH] D119010: [AggressiveInstCombine] Recognize table-based ctz implementation and enable it for AARCH64 at -O3

[Wilco Dijkstra via Phabricator via llvm-commits]

Wilco1 added inline comments.


================
Comment at: llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp:501
+  auto ZeroTableElem = ConstData->getElementAsInteger(0);
+  bool DefinedForZero = ZeroTableElem == InputBits;
+
----------------
This doesn't check that ZeroTableElem is either zero or InputBits (eg. if table[0] = 1 in ctz2 below, it has to be rejected). Also does it avoid emitting the AND if it is InputBits?

int ctz2 (unsigned x)
{
  const int u = 0;
  static short table[64] =
    {
      32, 0, 1,12, 2, 6, u,13, 3, u, 7, u, u, u, u,14,
      10, 4, u, u, 8, u, u,25, u, u, u, u, u,21,27,15,
      31,11, 5, u, u, u, u, u, 9, u, u,24, u, u,20,26,
      30, u, u, u, u,23, u,19,29, u,22,18,28,17,16, u
    };

  x = (x & -x) * 0x0450FBAF;
  return table[x >> 26];
}


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  https://reviews.llvm.org/D119010/new/

https://reviews.llvm.org/D119010