[PATCH] D116931: [GlobalISel][Legalizer] Support reducing load/store width in big endian order
Sheng via Phabricator via llvm-commits
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Mon Feb 7 06:01:34 PST 2022
0x59616e updated this revision to Diff 406417.
0x59616e added a comment.
Address feedback from @RKSimon. Thanks !
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D116931/new/
https://reviews.llvm.org/D116931
Files:
llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
llvm/test/CodeGen/M68k/GlobalISel/legalize-load-store.mir
Index: llvm/test/CodeGen/M68k/GlobalISel/legalize-load-store.mir
===================================================================
--- llvm/test/CodeGen/M68k/GlobalISel/legalize-load-store.mir
+++ llvm/test/CodeGen/M68k/GlobalISel/legalize-load-store.mir
@@ -78,16 +78,16 @@
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
- ; CHECK-NEXT: G_STORE [[C]](s32), [[LOAD]](p0) :: (store (s32), align 16)
- ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
+ ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[LOAD]], [[C4]](s32)
- ; CHECK-NEXT: G_STORE [[C1]](s32), [[PTR_ADD]](p0) :: (store (s32) into unknown-address + 4)
+ ; CHECK-NEXT: G_STORE [[C]](s32), [[PTR_ADD]](p0) :: (store (s32) into unknown-address + 12)
; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[LOAD]], [[C5]](s32)
- ; CHECK-NEXT: G_STORE [[C2]](s32), [[PTR_ADD1]](p0) :: (store (s32) into unknown-address + 8, align 8)
- ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
+ ; CHECK-NEXT: G_STORE [[C1]](s32), [[PTR_ADD1]](p0) :: (store (s32) into unknown-address + 8, align 8)
+ ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[LOAD]], [[C6]](s32)
- ; CHECK-NEXT: G_STORE [[C3]](s32), [[PTR_ADD2]](p0) :: (store (s32) into unknown-address + 12)
+ ; CHECK-NEXT: G_STORE [[C2]](s32), [[PTR_ADD2]](p0) :: (store (s32) into unknown-address + 4)
+ ; CHECK-NEXT: G_STORE [[C3]](s32), [[LOAD]](p0) :: (store (s32), align 16)
; CHECK-NEXT: RTS
%1:_(p0) = G_FRAME_INDEX %fixed-stack.0
%0:_(p0) = G_LOAD %1(p0) :: (load (p0) from %fixed-stack.0, align 8)
Index: llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
===================================================================
--- llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -4096,13 +4096,14 @@
// is a load, return the new registers in ValRegs. For a store, each elements
// of ValRegs should be PartTy. Returns the next offset that needs to be
// handled.
+ bool isBigEndian = MIRBuilder.getDataLayout().isBigEndian();
auto MMO = LdStMI.getMMO();
auto splitTypePieces = [=](LLT PartTy, SmallVectorImpl<Register> &ValRegs,
- unsigned Offset) -> unsigned {
+ unsigned NumParts, unsigned Offset) -> unsigned {
MachineFunction &MF = MIRBuilder.getMF();
unsigned PartSize = PartTy.getSizeInBits();
for (unsigned Idx = 0, E = NumParts; Idx != E && Offset < TotalSize;
- Offset += PartSize, ++Idx) {
+ ++Idx) {
unsigned ByteOffset = Offset / 8;
Register NewAddrReg;
@@ -4118,16 +4119,19 @@
} else {
MIRBuilder.buildStore(ValRegs[Idx], NewAddrReg, *NewMMO);
}
+ Offset = isBigEndian ? Offset - PartSize : Offset + PartSize;
}
return Offset;
};
- unsigned HandledOffset = splitTypePieces(NarrowTy, NarrowRegs, 0);
+ unsigned Offset = isBigEndian ? TotalSize - NarrowTy.getSizeInBits() : 0;
+ unsigned HandledOffset =
+ splitTypePieces(NarrowTy, NarrowRegs, NumParts, Offset);
// Handle the rest of the register if this isn't an even type breakdown.
if (LeftoverTy.isValid())
- splitTypePieces(LeftoverTy, NarrowLeftoverRegs, HandledOffset);
+ splitTypePieces(LeftoverTy, NarrowLeftoverRegs, NumLeftover, HandledOffset);
if (IsLoad) {
insertParts(ValReg, ValTy, NarrowTy, NarrowRegs,
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