[PATCH] D119060: [InstCombine] SimplifyDemandedBits - mul(x, x) is odd iff x is odd

[Sanjay Patel via Phabricator via llvm-commits]

spatel added inline comments.


================
Comment at: llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp:550-556
+        // X * X is odd iff X is odd.
+        if (DemandedMask == 1)
+          return I->getOperand(0);
+
+        // 'Quadratic Reciprocity': mul(x,x) -> 0 if we're only demanding bit[1]
+        if (DemandedMask == 2)
+          return ConstantInt::getNullValue(VTy);
----------------
lebedev.ri wrote:
> lebedev.ri wrote:
> > Can we generalize this to something along the lines of:
> > if we only demand 2 low bits, then replace with `and %x, 0b00001` ?
> https://alive2.llvm.org/ce/z/C2ihC2
Yes, that does seem better. I'll go ahead and commit this patch as a minimum improvement, then update with more tests and fix up the code to reduce risk.


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  https://reviews.llvm.org/D119060/new/

https://reviews.llvm.org/D119060