[PATCH] D118595: [AARCH64][DAGCombine] Add combine for negation of CSEL absolute value pattern.

[Dave Green via Phabricator via llvm-commits]

dmgreen added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:14699
 
+static bool isNegatedInteger(const SDValue &Op) {
+  return Op.getOpcode() == ISD::SUB && isNullConstant(Op.getOperand(0));
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SDValues can be passed by value - they are pretty small.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:14718
+static SDValue performNegCSelCombine(SDNode *N, SelectionDAG &DAG) {
+  if (N->getOpcode() != ISD::SUB || !isNullConstant(N->getOperand(0)))
+    return SDValue();
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Could this now use: `if (!isNegatedInteger(N))`?


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Comment at: llvm/test/CodeGen/AArch64/neg-selects.ll:1
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64-none-none-eabi %s -o - | FileCheck %s
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Can you pre-commit the tests and show just the differences here?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D118595/new/

https://reviews.llvm.org/D118595