[PATCH] D119115: [RISCV] Improve insert_vector_elt for fixed mask registers.

[Jianjian Guan via Phabricator via llvm-commits]

jacquesguan created this revision.
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Now the backend promotes mask vector to an i8 vector and insert element to that. We could bitcast to a widen element vector, and extract from it to GPR, then use I instruction to set the certain bit, and insert back to the widen element vector.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D119115

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-i1.ll

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