[PATCH] D119110: [RISCV] support vwmulsu_vx when one input is a scalar splat

[Chenbing.Zheng via Phabricator via llvm-commits]

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If one input of a fixed vector multiply is a sign extend and
the other operand is a splat of a scalar,  we can use vwmulsu_vx
if the scalar value has sufficient zero bits.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D119110

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulsu.ll

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