[PATCH] D118415: AMDGPU: Reserve v32 if we may need to copy between AGPRs on gfx908

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp:601
+  } else {
+    Tmp = RS.scavengeRegister(&AMDGPU::VGPR_32RegClass, 0);
   }
----------------
rampitec wrote:
> rampitec wrote:
> > It misses error reporting and setRegUsed call.
> Ping.
The error reporting was pointless because if !AllowSpill, scavengeRegister emits the error


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https://reviews.llvm.org/D118415