[PATCH] D119089: [RISCV] Teach RISCVDAGToDAGISel::selectShiftMask to replace sub from constant with neg.

[Craig Topper via Phabricator via llvm-commits]

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If the shift amount is (sub C, X) where C is 0 modulo the size of
the shift, we can replace it with neg or negw.

Similar is is done for AArch64 and X86.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D119089

Files:
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/test/CodeGen/RISCV/rotl-rotr.ll
  llvm/test/CodeGen/RISCV/shifts.ll

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