[llvm] c35ccd2 - [DAGCombiner][RISCV] Allow rotates by non-constant to be matched for i32 on riscv64 with Zbb.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sun Feb 6 10:58:18 PST 2022
Author: Craig Topper
Date: 2022-02-06T10:58:12-08:00
New Revision: c35ccd2ac852bec22c5eafb65bf0e9adb1451df0
URL: https://github.com/llvm/llvm-project/commit/c35ccd2ac852bec22c5eafb65bf0e9adb1451df0
DIFF: https://github.com/llvm/llvm-project/commit/c35ccd2ac852bec22c5eafb65bf0e9adb1451df0.diff
LOG: [DAGCombiner][RISCV] Allow rotates by non-constant to be matched for i32 on riscv64 with Zbb.
rv64izbb has a RORW/ROLW instructions that operate on the lower
32-bits of a 64-bit value and sign extend bit 31 of the result.
DAGCombiner won't match rotate idioms because the i32 type isn't Legal
on riscv64.
This patch teaches DAGCombiner to allow it if the type is going to
be promoted and the target has Custom type legalization for ISD::ROTL
or ISD::ROTR. I've restricted this to scalar types. It doesn't appear
any in tree targets other than riscv64 have custom type legalization
for rotates.
If this patch isn't acceptable, I guess I can match SRLW, SLLW, and OR
after type legalization, but I'd like to avoid that if possible.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D119062
Added:
Modified:
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/test/CodeGen/RISCV/rotl-rotr.ll
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 08450f77986b8..2b0d476dbc5ab 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -583,11 +583,11 @@ namespace {
bool DemandHighBits = true);
SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1);
SDValue MatchRotatePosNeg(SDValue Shifted, SDValue Pos, SDValue Neg,
- SDValue InnerPos, SDValue InnerNeg,
+ SDValue InnerPos, SDValue InnerNeg, bool HasPos,
unsigned PosOpcode, unsigned NegOpcode,
const SDLoc &DL);
SDValue MatchFunnelPosNeg(SDValue N0, SDValue N1, SDValue Pos, SDValue Neg,
- SDValue InnerPos, SDValue InnerNeg,
+ SDValue InnerPos, SDValue InnerNeg, bool HasPos,
unsigned PosOpcode, unsigned NegOpcode,
const SDLoc &DL);
SDValue MatchRotate(SDValue LHS, SDValue RHS, const SDLoc &DL);
@@ -7031,8 +7031,9 @@ static bool matchRotateSub(SDValue Pos, SDValue Neg, unsigned EltSize,
// Neg with outer conversions stripped away.
SDValue DAGCombiner::MatchRotatePosNeg(SDValue Shifted, SDValue Pos,
SDValue Neg, SDValue InnerPos,
- SDValue InnerNeg, unsigned PosOpcode,
- unsigned NegOpcode, const SDLoc &DL) {
+ SDValue InnerNeg, bool HasPos,
+ unsigned PosOpcode, unsigned NegOpcode,
+ const SDLoc &DL) {
// fold (or (shl x, (*ext y)),
// (srl x, (*ext (sub 32, y)))) ->
// (rotl x, y) or (rotr x, (sub 32, y))
@@ -7043,7 +7044,6 @@ SDValue DAGCombiner::MatchRotatePosNeg(SDValue Shifted, SDValue Pos,
EVT VT = Shifted.getValueType();
if (matchRotateSub(InnerPos, InnerNeg, VT.getScalarSizeInBits(), DAG,
/*IsRotate*/ true)) {
- bool HasPos = TLI.isOperationLegalOrCustom(PosOpcode, VT);
return DAG.getNode(HasPos ? PosOpcode : NegOpcode, DL, VT, Shifted,
HasPos ? Pos : Neg);
}
@@ -7059,8 +7059,9 @@ SDValue DAGCombiner::MatchRotatePosNeg(SDValue Shifted, SDValue Pos,
// TODO: Merge with MatchRotatePosNeg.
SDValue DAGCombiner::MatchFunnelPosNeg(SDValue N0, SDValue N1, SDValue Pos,
SDValue Neg, SDValue InnerPos,
- SDValue InnerNeg, unsigned PosOpcode,
- unsigned NegOpcode, const SDLoc &DL) {
+ SDValue InnerNeg, bool HasPos,
+ unsigned PosOpcode, unsigned NegOpcode,
+ const SDLoc &DL) {
EVT VT = N0.getValueType();
unsigned EltBits = VT.getScalarSizeInBits();
@@ -7072,7 +7073,6 @@ SDValue DAGCombiner::MatchFunnelPosNeg(SDValue N0, SDValue N1, SDValue Pos,
// (srl x1, (*ext y))) ->
// (fshr x0, x1, y) or (fshl x0, x1, (sub 32, y))
if (matchRotateSub(InnerPos, InnerNeg, EltBits, DAG, /*IsRotate*/ N0 == N1)) {
- bool HasPos = TLI.isOperationLegalOrCustom(PosOpcode, VT);
return DAG.getNode(HasPos ? PosOpcode : NegOpcode, DL, VT, N0, N1,
HasPos ? Pos : Neg);
}
@@ -7134,6 +7134,16 @@ SDValue DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, const SDLoc &DL) {
bool HasROTR = hasOperation(ISD::ROTR, VT);
bool HasFSHL = hasOperation(ISD::FSHL, VT);
bool HasFSHR = hasOperation(ISD::FSHR, VT);
+
+ // If the type is going to be promoted and the target has enabled custom
+ // lowering for rotate, allow matching rotate by non-constants. Only allow
+ // this for scalar types.
+ if (VT.isScalarInteger() && TLI.getTypeAction(*DAG.getContext(), VT) ==
+ TargetLowering::TypePromoteInteger) {
+ HasROTL |= TLI.getOperationAction(ISD::ROTL, VT) == TargetLowering::Custom;
+ HasROTR |= TLI.getOperationAction(ISD::ROTR, VT) == TargetLowering::Custom;
+ }
+
if (LegalOperations && !HasROTL && !HasROTR && !HasFSHL && !HasFSHR)
return SDValue();
@@ -7276,26 +7286,26 @@ SDValue DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, const SDLoc &DL) {
if (IsRotate && (HasROTL || HasROTR)) {
SDValue TryL =
MatchRotatePosNeg(LHSShiftArg, LHSShiftAmt, RHSShiftAmt, LExtOp0,
- RExtOp0, ISD::ROTL, ISD::ROTR, DL);
+ RExtOp0, HasROTL, ISD::ROTL, ISD::ROTR, DL);
if (TryL)
return TryL;
SDValue TryR =
MatchRotatePosNeg(RHSShiftArg, RHSShiftAmt, LHSShiftAmt, RExtOp0,
- LExtOp0, ISD::ROTR, ISD::ROTL, DL);
+ LExtOp0, HasROTR, ISD::ROTR, ISD::ROTL, DL);
if (TryR)
return TryR;
}
SDValue TryL =
MatchFunnelPosNeg(LHSShiftArg, RHSShiftArg, LHSShiftAmt, RHSShiftAmt,
- LExtOp0, RExtOp0, ISD::FSHL, ISD::FSHR, DL);
+ LExtOp0, RExtOp0, HasFSHL, ISD::FSHL, ISD::FSHR, DL);
if (TryL)
return TryL;
SDValue TryR =
MatchFunnelPosNeg(LHSShiftArg, RHSShiftArg, RHSShiftAmt, LHSShiftAmt,
- RExtOp0, LExtOp0, ISD::FSHR, ISD::FSHL, DL);
+ RExtOp0, LExtOp0, HasFSHR, ISD::FSHR, ISD::FSHL, DL);
if (TryR)
return TryR;
diff --git a/llvm/test/CodeGen/RISCV/rotl-rotr.ll b/llvm/test/CodeGen/RISCV/rotl-rotr.ll
index 553d0b81b63df..75943edf4187e 100644
--- a/llvm/test/CodeGen/RISCV/rotl-rotr.ll
+++ b/llvm/test/CodeGen/RISCV/rotl-rotr.ll
@@ -40,11 +40,7 @@ define i32 @rotl_32(i32 %x, i32 %y) nounwind {
;
; RV64ZBB-LABEL: rotl_32:
; RV64ZBB: # %bb.0:
-; RV64ZBB-NEXT: li a2, 32
-; RV64ZBB-NEXT: subw a2, a2, a1
-; RV64ZBB-NEXT: sllw a1, a0, a1
-; RV64ZBB-NEXT: srlw a0, a0, a2
-; RV64ZBB-NEXT: or a0, a1, a0
+; RV64ZBB-NEXT: rolw a0, a0, a1
; RV64ZBB-NEXT: ret
%z = sub i32 32, %y
%b = shl i32 %x, %y
@@ -79,11 +75,7 @@ define i32 @rotr_32(i32 %x, i32 %y) nounwind {
;
; RV64ZBB-LABEL: rotr_32:
; RV64ZBB: # %bb.0:
-; RV64ZBB-NEXT: li a2, 32
-; RV64ZBB-NEXT: subw a2, a2, a1
-; RV64ZBB-NEXT: srlw a1, a0, a1
-; RV64ZBB-NEXT: sllw a0, a0, a2
-; RV64ZBB-NEXT: or a0, a1, a0
+; RV64ZBB-NEXT: rorw a0, a0, a1
; RV64ZBB-NEXT: ret
%z = sub i32 32, %y
%b = lshr i32 %x, %y
@@ -322,10 +314,7 @@ define i32 @rotl_32_mask(i32 %x, i32 %y) nounwind {
;
; RV64ZBB-LABEL: rotl_32_mask:
; RV64ZBB: # %bb.0:
-; RV64ZBB-NEXT: negw a2, a1
-; RV64ZBB-NEXT: sllw a1, a0, a1
-; RV64ZBB-NEXT: srlw a0, a0, a2
-; RV64ZBB-NEXT: or a0, a1, a0
+; RV64ZBB-NEXT: rolw a0, a0, a1
; RV64ZBB-NEXT: ret
%z = sub i32 0, %y
%and = and i32 %z, 31
@@ -359,10 +348,7 @@ define i32 @rotr_32_mask(i32 %x, i32 %y) nounwind {
;
; RV64ZBB-LABEL: rotr_32_mask:
; RV64ZBB: # %bb.0:
-; RV64ZBB-NEXT: negw a2, a1
-; RV64ZBB-NEXT: srlw a1, a0, a1
-; RV64ZBB-NEXT: sllw a0, a0, a2
-; RV64ZBB-NEXT: or a0, a1, a0
+; RV64ZBB-NEXT: rorw a0, a0, a1
; RV64ZBB-NEXT: ret
%z = sub i32 0, %y
%and = and i32 %z, 31
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