[llvm] d3f966c - [AArch64] LowerVectorSRA_SRL_SHL - silence dead code warning

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2022-02-06T16:29:38Z
New Revision: d3f966c6f02f4438d35ade0f0e802739c0802e2d

URL: https://github.com/llvm/llvm-project/commit/d3f966c6f02f4438d35ade0f0e802739c0802e2d
DIFF: https://github.com/llvm/llvm-project/commit/d3f966c6f02f4438d35ade0f0e802739c0802e2d.diff

LOG: [AArch64] LowerVectorSRA_SRL_SHL - silence dead code warning

Remove default case from switch and move llvm_unreachable to after the switch()

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 4362bc04a35c7..f0813f1f7c61d 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -11353,9 +11353,6 @@ SDValue AArch64TargetLowering::LowerVectorSRA_SRL_SHL(SDValue Op,
   unsigned EltSize = VT.getScalarSizeInBits();
 
   switch (Op.getOpcode()) {
-  default:
-    llvm_unreachable("unexpected shift opcode");
-
   case ISD::SHL:
     if (VT.isScalableVector() || useSVEForFixedLengthVectorVT(VT))
       return LowerToPredicatedOp(Op, DAG, AArch64ISD::SHL_PRED);
@@ -11398,7 +11395,7 @@ SDValue AArch64TargetLowering::LowerVectorSRA_SRL_SHL(SDValue Op,
     return NegShiftLeft;
   }
 
-  return SDValue();
+  llvm_unreachable("unexpected shift opcode");
 }
 
 static SDValue EmitVectorComparison(SDValue LHS, SDValue RHS,