[PATCH] D118765: [DAGCombiner] Fold SSHLSAT/USHLSAT to SHL when no saturation will occur

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

a few minors



================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:9371
+    if (N->getOpcode() == ISD::SSHLSAT && N1C &&
+        DAG.ComputeNumSignBits(N0) > N1C->getZExtValue())
+      return DAG.getNode(ISD::SHL, SDLoc(N), VT, N0, N1);
----------------
We've been hit in the past by fuzzers which think its funny to create constants greater than i64 - so maybe:
```
N1->getAPIntValue().ult(DAG.ComputeNumSignBits(N0))
```


================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:9376
+    if (N->getOpcode() == ISD::USHLSAT && N1C &&
+        BitWidth > N1C->getZExtValue() &&
+        DAG.MaskedValueIsZero(
----------------
```
N1->getAPIntValue().ult(BitWidth) &&
```


================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:9378
+        DAG.MaskedValueIsZero(
+            N0, APInt::getHighBitsSet(BitWidth, N1C->getZExtValue())))
+      return DAG.getNode(ISD::SHL, SDLoc(N), VT, N0, N1);
----------------
It might be easier to grok as this?
```
DAG.computeKnownBits(N0).getMaxValue().ult(N1C->getZExtValue())
```


Repository:
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  https://reviews.llvm.org/D118765/new/

https://reviews.llvm.org/D118765