[llvm] f3a725a - [RISCV] Add signext test for llvm.abs.i32 for rv64 Zbb.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-02-05T21:26:47-08:00
New Revision: f3a725af43b34df227745d7f8c531f4751d7a37c

URL: https://github.com/llvm/llvm-project/commit/f3a725af43b34df227745d7f8c531f4751d7a37c
DIFF: https://github.com/llvm/llvm-project/commit/f3a725af43b34df227745d7f8c531f4751d7a37c.diff

LOG: [RISCV] Add signext test for llvm.abs.i32 for rv64 Zbb.

This shows that we don't preserve sign bits across the
abs expansion, but I think we could if we used negw+max.

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/rv64zbb.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/RISCV/rv64zbb.ll b/llvm/test/CodeGen/RISCV/rv64zbb.ll
index db249e9f22c04..27d2a232c5c91 100644
--- a/llvm/test/CodeGen/RISCV/rv64zbb.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zbb.ll
@@ -956,6 +956,26 @@ define i32 @abs_i32(i32 %x) {
   ret i32 %abs
 }
 
+; FIXME: We can remove the sext.w by using addw for RV64I and negw for RV64ZBB.
+define signext i32 @abs_i32_sext(i32 signext %x) {
+; RV64I-LABEL: abs_i32_sext:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    srai a1, a0, 63
+; RV64I-NEXT:    add a0, a0, a1
+; RV64I-NEXT:    xor a0, a0, a1
+; RV64I-NEXT:    sext.w a0, a0
+; RV64I-NEXT:    ret
+;
+; RV64ZBB-LABEL: abs_i32_sext:
+; RV64ZBB:       # %bb.0:
+; RV64ZBB-NEXT:    neg a1, a0
+; RV64ZBB-NEXT:    max a0, a0, a1
+; RV64ZBB-NEXT:    sext.w a0, a0
+; RV64ZBB-NEXT:    ret
+  %abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true)
+  ret i32 %abs
+}
+
 declare i64 @llvm.abs.i64(i64, i1 immarg)
 
 define i64 @abs_i64(i64 %x) {